Phison Electronics Corporation

An-Cheng Liu

Wei Hung Lin

Yu-Siang Yang

Yu-Cheng Hsu

Szu-Wei Chen

Yu-Heng Liu

Siu-Tung Lam

Chun-Hsi Lai

Ting-Chien Zhan

Shih-Jia Zeng

Lih Yuarn Ou

Tsai-Hao Kuo

Yao-Hsuan Li

A data accessing method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a codeword stored in a physical programming unit, and calculating a bit change ratio of a bit value change in dummy data included in the codeword; adjusting a read voltage level or a log likelihood ratio according to the bit change ratio; and performing a decoding operation on the codeword by using the adjusted read voltage level or the adjusted log likelihood ratio.

Method for adjusting a read voltage level or log likelihood ratio of a memory based on a calculated bit change ratio, memory controlling circuit unit, and memory storage device

A memory management method, a memory storage apparatus and a memory control circuit unit are disclosed. The method includes: sending a plurality of read command sequences including a first read command sequence and a second read command sequence, and the first read command sequence is configured to instruct a performing of a first read operation on a first physical unit of a rewritable non-volatile memory module, and the second read command sequence is configured to instruct a performing of a second read operation on the first physical unit; determining a system parameter according to a time interval between a first read time point corresponding to the first read operation and a second read time point corresponding to the second read operation; and instructing the rewritable non-volatile memory module to perform a specific operation according to the system parameter.

Memory management method, memory storage apparatus and memory control circuit unit

A data reading method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: receiving a read command from a host system, and the read command instructs reading data from at least one logical unit, and the logical unit is mapped to a first physical unit; obtaining state information of at least two neighboring memory cells in the first physical unit; determining an electrical parameter offset value corresponding to the neighboring memory cells according to the state information; and sending a read command sequence according to the electrical parameter offset value, and the read command sequence instructs reading the first physical unit based on at least one electrical parameter, and the electrical parameter is controlled by the electrical parameter offset value.

Data reading method, memory storage device, and memory control circuit unit

A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to first management information among multiple candidate management information; decoding the first data and recording first error bit information of the first data; and adjusting sorting information related to the candidate management information according to the first error bit information. The sorting information reflects a usage order of the candidate management information in a decoding operation.

Memory management method, memory storage device, and memory control circuit unit

A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: programming multiple first memory cells in a first physical erasing unit in a rewritable non-volatile memory module; and applying an electronic pulse to at least one word line in the rewritable non-volatile memory module. The at least one word line is coupled to multiple second memory cells in the first physical erasing unit. The second memory cells include the first memory cells. The electronic pulse is not configured to read, program, or erase the second memory cells.

Memory control method, memory storage device, and memory control circuit unit

A flash memory control method, a flash memory storage device and a flash memory controller are provided. The method includes the following. A flash memory module is instructed to perform a data merge operation to copy first data in a first physical unit into at least one second physical unit. After the first data is copied and before the first physical unit is erased, another programming operation is performed on the first physical unit to change a data storage state of at least a part of memory cells in the first physical unit from a first state into a second state. After the first physical unit is programmed, an erase operation is performed on the first physical unit.

Flash memory control method of re-programming memory cells before erase operations, flash memory storage device and flash memory controller

A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading a first physical unit based on a first read voltage level to obtain first data; reading the first physical unit based on a second read voltage level to obtain second data; reading the first physical unit based on a third read voltage level to obtain third data; obtaining a first reference value which reflects a data variation status between the first data and the second data; obtaining a second reference value which reflects a data variation status between the first data and the third data; reading the first physical unit based on a fourth read voltage level to obtain fourth data according to the first reference value and the second reference value; and decoding the fourth data by a decoding circuit.

Adjusting read voltage level in rewritable nonvolatile memory module

A voltage identifying method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a plurality of first memory cells according to a first read voltage group in a plurality of read voltage groups and performing a first decoding operation to generate first verification information; identifying a plurality of second read voltage groups in the plurality of read voltage groups corresponding to a first interval in a plurality of intervals according to the first interval in which the first verification information is located; and reading the plurality of first memory cells by using a third read voltage group in the plurality of second read voltage groups and performing the first decoding operation.

Voltage identifying method, memory controlling circuit unit and memory storage device

A memory control method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit of a rewritable non-volatile memory module; decoding the first data by a decoding circuit; updating reliability information according to the decoded first data; reading second data from a second physical unit of the rewritable non-volatile memory module; and decoding the second data by the decoding circuit according to the updated reliability information.

Memory control method, memory storage device and memory control circuit unit

A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: programming first data into a plurality of first memory cells in the rewritable non-volatile memory module, such that the programmed first memory cells have a plurality of states; sending a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level; obtaining first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence; and adjusting the first read voltage level according to the first count information and default count information corresponding to the first read voltage level.

Memory management method, memory storage device and memory control circuit unit

A bit determining method, a memory control circuit unit and a memory storage device are provided. The method includes: reading a first storage state of a first memory cell to obtain a first value of a first significant bit; reading the first storage state of the first memory cell to obtain at least one second value of at least one second significant bit; performing a first decoding operation according to the at least one second value to obtain at least one third value of the decoded second significant bit; determining whether the first significant bit is a special bit according to the first storage state and a second storage state corresponding to the at least one third value; and if the first significant bit is the special bit, performing a corresponding decoding operation.

Bit determining method, memory control circuit unit and memory storage device

A data accessing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit by using a first read voltage to obtain first data; reading the first physical programming unit by using a second read voltage to obtain second data; inputting a first state parameter corresponding to the first data and a second state parameter corresponding to the second data into a numerical calculation engine, and determining a third reading voltage for reading the first physical programming unit by the numerical calculation engine.

Data accessing method, memory controlling circuit unit and memory storage device

A read voltage tracking method, a memory storage device and a memory control circuit unit are provided. The method includes obtaining a plurality of test read voltages corresponding to a plurality of voltage adjustment values, and obtaining an optimal read voltage according to the voltage adjustment values. The step of obtaining the test read voltages includes obtaining a second test read voltage by adjusting a first test read voltage according to a first voltage adjustment value, and obtaining a third test read voltage by adjusting the second test read voltage according to a second voltage adjustment value, and the first test read voltage is a preset test read voltage, the first voltage adjustment value is a preset voltage adjustment value, and the first voltage adjustment value is different from the second voltage adjustment value.

Read voltage tracking method, memory storage device and memory control circuit unit

The present disclosure provides a memory management method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes physical programming units, each of which includes multiple bits. The memory management method includes: identifying a first physical programming unit by applying a predetermined read voltage, where the first physical programming unit is identified as in a fully-erased status; identifying a second and a third physical programming units which are programmed before the first physical programming unit; acquiring status data of the second and the third physical programming unit; computing a difference of the status data between the second and the third physical programming unit; if the difference is larger than a threshold, identifying the second physical programming unit as in a program failure status.

Memory management method, memory control circuit unit and memory storage apparatus

A memory programming method for a rewritable non-volatile memory module having memory cells is provided. The memory programming method includes: performing a first programming process on the memory cells according to write data and obtaining a first programming result of the first programming process; grouping the memory cells into programming groups according to the first programming result; and performing a second programming process on the memory cells according to the write data. The second programming process includes: programming a first programming group among the programming groups by using a first program voltage; and programming a second programming group among the programming groups by using a second program voltage. The first program voltage and the second program voltage are different. Moreover, a memory control circuit unit and a memory storage device are provided.

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Taipei, Taiwan

An-Cheng Liu