Spansion Llc.

Globalfoundries Inc.

Advanced Micro Devices Corporation

An Chen

Zoran Krivokapic

Sameer S Haddad

Steven C Avanzino

Suzette Keefe Pangrle

Manuj Rathor

Yi-Ching Jean Wu

Matthew S Buynoski

Nicholas H Tripsas

Swaroop Kaza

Tzu-Ning Fang

Jeffrey Allan Shields

Kuo-Tung Chang

Colin Stewart Bill

Wei Zheng

Zhizheng Liu

Ashot Melik-Martirosian

Sung-Yong Chung

Gulzar Ahmed Kathawala

At least one method, apparatus and system disclosed involves providing a restricted access protocol for accessing a memory device. A first memory portion of a memory device is selected for providing an access confirmation. At least one of setting or resetting of memory cells of the first memory portion is performed. A first voltage is provided for switching the memory cells. The first voltage is associated with a predetermined switching probability. A first input signal comprising at least one address associated with the memory cells is provided. A first responsive signal is received in response to the input signal. The first responsive signal comprises data relating to the state of the memory cells. An access key is provided for the access confirmation based upon a relationship between the first input signal and the first responsive signals for providing an access key.

Method, apparatus and system for security application for integrated circuit devices

Embodiments of non-volatile random access memory (RAM) devices and methods of forming the same are provided herein. In an embodiment, a non-volatile RAM device includes a first access transistor that is in electrical communication with a wordline. A first memory element and a first two-terminal selector are serially connected to each other and are in electrical communication with a first bitline and the first access transistor. A second memory element and a second two-terminal selector are serially connected to each other and are in electrical communication with a second bitline and the first access transistor.

Non-volatile random access memory devices with shared transistor configuration and methods of forming the same

In an electronic device, a diode and a resistive memory device are connected in series. The diode may take a variety of forms, including oxide or silicon layers, and one of the layers of the diode may make up a layer of the resistive memory device which is in series with that diode.

Diode and resistive memory device structures

Methods and apparatus are provided for storing data in a non-volatile memory device. A method includes comparing bits of a write instruction with bits in a memory block to determine bits to be switched in the memory block; determining a switch type for each bit to be switched in the memory block; and evaluating the switch type for each bit to be switched in the memory block. The method further comprises when at least one switch type is a first switch type, performing a first operation on the memory block, and when all of the switch types are not the first switch type, performing a second operation on each bit to be switched in the memory block.

Methods and systems for memory devices with asymmetric switching characteristics

Apparatus and related fabrication and read methods are provided for crossbar memory elements. An exemplary crossbar memory element includes a crossbar array structure including a set of access lines, unswitched resistance elements coupled electrically in series between the set of access lines and a reference voltage node, and switched resistance elements coupled electrically in series between the first set of access lines and the reference voltage node. To read from a selected access line, the switched resistance element associated with that access line is enabled while the remaining switched resistance elements are disabled.

Crossbar array memory elements and related read methods

A chain of field coupled nanomagnets includes at least one elements having substantially different anisotropy energy from that of the other nanomagnets. A signal can propagate from a first input nanomagnet having a relatively high anisotropy energy through the chain to an output nanomagnet. The output nanomagnet may have a relatively lower anisotropy energy than the other nanomagnets. Signal flow direction thus can be controlled. The higher anisotropy energy nanomagnet may be attained by use of a ferromagnet material having a higher anisotropy constant and/or configured with a larger volume than the other elements. The lower anisotropy energy magnet may be attained by use of a ferromagnet material having a lower anisotropy constant and/or configured with a smaller volume than the other elements. Logic signal flow control can also be attained making use of three dimensional geometries of nanomagnets with two different orientations.

Signal control elements in ferromagnetic logic

A device is provided that includes a structure having a sidewall surface, a layer of material provided on the sidewall surface, and a device structure provided in contact with the layer of material. Fabrication techniques includes a process that includes forming a structure having a sidewall surface, forming a layer of material on the sidewall surface, and forming a device structure in contact with the layer of material, where the device structure and the layer of material are components of a device.

Sidewall graphene devices for 3-D electronics

Apparatus and related fabrication and operating methods are provided for logic circuits that include ferromagnetic elements. An exemplary logic circuit includes a first ferromagnetic element having a first ferromagnetic layer, a second ferromagnetic element having a second ferromagnetic layer, and a transistor coupled to the first ferromagnetic element. The first transistor is configured to allow current to flow through the first ferromagnetic element. The current influences the magnetization direction of the first ferromagnetic layer, which, in turn, influences the magnetization direction of the second ferromagnetic layer.

Nonvolatile CMOS-compatible logic circuits and related operating methods

In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto.

Test structures for development of metal-insulator-metal (MIM) devices

A process is provided that includes forming a first mask on an underlying layer, where the mask has two adjacent portions with an open gap therebetween, and depositing a second mask material within the open gap and at an inclined angle with respect to an upper surface of the underlying layer to form a second mask. In another implementation, a process is provided that includes forming a first mask on an underlying layer, where the mask has a pattern that includes an open gap, and depositing a second mask material within the open gap to form a second mask, where particles of the second mask material are directed in parallel or substantially in parallel to a line at an inclined angle with respect to an upper surface of the underlying layer.

Process of patterning small scale devices

In a first method of erasing a resistive memory device, an electrical potential is applied to the gate of a transistor in series with the resistive memory device, and successive increasing currents are provided through the resistive memory device by means of providing successive increasing electrical potentials across the resistive memory device. In a second method of erasing a resistive memory device, an electrical potential is applied across the resistive memory device, and successive increasing currents are provided through the resistive memory device by means of providing successive increasing electrical potentials to the gate of a transistor in series with the resistive memory device.

Method of erasing a resistive memory device

A graphene-based device is formed with a substrate having a trench therein, a device structure on the substrate and within the trench, a graphene layer over the device structure, and a protective layer over the graphene layer. Fabrication techniques include forming a trench in a substrate, forming a device structure within the trench, forming a graphene layer over the device structure, and forming a protective layer over the graphene layer.

Growing community of inventors

Sunnyvale, CA, United States of America

An Chen