Synopsys, Inc.

Magma Design Automation, Inc.

Amzie Adams

Alessandra Nardi

Piyush Verma

Joseph R Walston

Pranay Prakash

Thomas Andersen

Joe Walston

Mehrdad Najibi

A method includes generating a plurality of intermediate designs for a chip by executing a first sub-step based on a first plurality of inputs, adding at least one intermediate design of the plurality of intermediate designs to a second plurality of inputs, generating a plurality of final designs by executing a second sub-step of the step of the design flow based on the second plurality of inputs, and selecting using a machine learning model a final design from the plurality of final designs. The first sub-step is a sub-step of a step of a design flow and the first plurality of inputs corresponds to input parameters associated with the first sub-step.

Dividing a chip design flow into sub-steps using machine learning

A method of electronic design automation (EDA) using machine learning to modify a current circuit design is provided. The method includes searching for data associated with previous design sessions for previous circuit designs, the searching being performed by implementing machine learning to identify similarities between the current circuit design and the previous circuit designs and the searching providing simulation data identifying the previous design sessions and simulation results of the previous design sessions, determining, in dependence on the simulation data, a respective degree of relevance between the current circuit design and the previous circuit designs, and performing a modification by applying the simulation data to the current circuit design based on the degree of relevance, the applying of the simulation data including performing simulations that apply values obtained from the simulation data to parameters related to the current circuit design and settings related to a simulation of the current design.

Modifying a current circuit design using data from one or more previous circuit designs identified as being similar to the current circuit design

A method and apparatus for aggregating multiple component metrics into a single reward function output value (AOV) is disclosed. The method comprises determining at least one component metric value to be used to determine the AOV. In addition, the method comprises determining at least one component metric target value to strive to achieve. Furthermore, the method comprises determining at least one baseline value to use when determining the AOV. Still further, the method comprises determining unacceptable values for particular component metrics. The method also comprises combining at least one component metric value into a single AOV and optimizing component input values to achieve the best AOV.

Aggregating multiple component metrics into a single reward function

A statistical on-chip variation approach to timing analysis permits the automated or semi-automated selection of design-specific margins without requiring complex statistical libraries. By separately addressing the impact of random and systematic variations on timing, a design-specific margin can be obtained and used in downstream OCV analysis. In addition, where statistical libraries are available for some portions of a design, these can be incrementally included in the timing analysis to obtain more accurate results.

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Raleigh, NC, United States of America

Amzie Adams