Intel Corporation

Amy Whitcombe

Brent R Carlton

Somnath Kundu

Stefano Pellerano

Chun Lee

Asma Beevi Kuriparambil Thekkumpate

An apparatus can include a digital-to-analog converter (DAC) and calibration circuitry including an oscillator. The calibration circuitry can be coupled to an output of the DAC, the calibration circuitry to sample and count DAC output pulses for at least two consecutive pulses using at least two separate counter circuits. The calibration circuitry can determine error between at least two consecutive pulses and provide a correction value based on the error. The apparatus can further include correction circuitry to provide a calibration signal to the DAC based on the correction value.

High-speed digital-to-analog converter calibration

An apparatus, system, and method for are provided. A device includes a time-to-digital converter (TDC) situated to convert a time-domain signal to a digital value, a delay circuit situated in parallel with the TDC and to delay the time-domain signal by a specified amount of time resulting in a delayed time-domain signal, a time-to-voltage converter (TVC) situated to produce a voltage-domain signal based on the delayed time-domain signal, and a successive approximation (SAR) circuit situated to receive the digital value and the voltage-domain signal and produce a digital-domain version of the input signal.

Time-domain assist for successive approximation ADC

A differential voltage-to-time converter (VTC) architecture and method of providing VTC signals are disclosed. The VTC includes a ramp generator that generates a ramp voltage, capacitors having a bottom plate coupled with the ramp generator to receive the ramp voltage, and inverters having inputs coupled to top plates of the capacitors to provide signals based on a sampled signal. A threshold voltage or supply voltage of the inverters tracks a minimum input signal voltage.

Low noise inverter-based voltage-to-time converter with common mode input tracking

A time-to-digital converter (TDC) that combines the energy efficiency of a successive approximation (SAR) design with the high speed of pipelined converters by leveraging the inherently pipelined nature of time-domain signaling. The TDC achieves high speed by removing a comparator decision from a signal path, instead using AND/OR gates to separate early and late edges. The TDC uses a pipelined SAR architecture to digitize a differential delay between two incoming clock edges with high speed and low power consumption. Described is a modular digital reference voltage generator that can be used for a capacitive digital-to-analog converter (DAC). The generator comprises a decoupling capacitor, one or more clocked comparators, and power transistor(s). A simplified digital low dropout (LDO) circuitry is used to provide fast reference voltage generation with minimal overhead. The LDO circuitry is arrayed using time-interleaved synchronous clocks or staggered asynchronous clocks to provide finer timing resolution.

Growing community of inventors

Saratoga, CA, United States of America

Amy Whitcombe