International Business Machines Corporation

Other

Amy May Tuvell

Robert Paul Masleid

Wolfgang Roesner

John Stephen Muhich

Kurt Alan Feiste

Byron Lee Krauter

Ronny Lee Arnold

Thomas Albert Petersen

Michael Alexander Bowen

Alexander Edward Okpisz

Clay Chip Smith

Tai Dinh Ngo

Steven Arthur Schmidt

A method for building a multiprocessor data processing system is disclosed. A component among a collection of components on a multichip module is identified. The collection of components, which includes both processors and cache components, and each of the components may be functional or non-functional. A determination is made as to whether or not the identified component is functional. In response to a determination that the identified component is functional, the process of component association is performed between the identified component and other functional components on the multichip module such that interconnect length between all functional components can be minimized.

Method and system for building a multiprocessor data processing system

An apparatus and method for determining power consumption in logic devices including mixed static and dynamic logic blocks is implemented. Input logical signals are tagged as having dynamical behavior or static behavior, and the power consumption of the logic block determined according to the behavior of the input signal. If an input signal has dynamic behavior, an output signal making a transition in response thereto will make two transitions per clock cycle, and the per cycle power consumption of the logic block is accordingly weighted. In another embodiment, a Boolean behavior signal is calculated for each block from clock phase tags and &ldquo;one cycle per cycle&rdquo; circuit level simulations. The per cycle power consumption of each logic block receives a weight in response to the Boolean behavior signal, according the behavior of the block characterized thereby.

Data processing system and method to estimate power in mixed dynamic/static CMOS designs

Storage access blocking instructions, such as the EIEIO instruction implemented within the PowerPC architecture, block other storage access instructions at the bus interface stage as opposed to the execute stage. Therefore, cacheable instructions, and other similar instructions, are allowed to complete without being blocked by such an EIEIO instruction not ordered by the EIEIO instruction.

System and method for interlocking barrier operations in load and store queues

In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address generation portion of the store instruction is executed within the load store unit, while the store data portion of the instruction is executed in an execution unit other than the load store unit. If the store instruction is a fixed point execution unit, then the store data portion is executed within the fixed point unit. If the store instruction is a floating point store instruction, then the store data portion of the store instruction is executed within the floating point unit. The store instruction is completed when all older instructions have completed and when all instructions in the instruction group have finished.

System and method for executing and completing store instructions

A domino logic simulator for a CMOS domino logic circuit seeds all logic circuits under test with an 'X' state before initialization of a special simulator machine cycle devoted to validating all pre-charge circuits in each stage of the CMOS domino logic circuit. In the special machine cycle, each stage of the circuit receives a discrete clock signal which is applied to the pre-charge and logic devices in precharge and evaluation phase sequences. The clock phase sequences in each stage propagate the 'X' state at each logic circuit through the succeeding stages to provide an 'X' output for the machine cycle, except a '0' state is provided as an output at the end of the machine cycle if the precharge circuit in each stage is functioning properly during the precharge sequences of the clock cycle applied to the stage. A clocked delay reset circuit in each stage provides the output of the stage. A static logic device in each stage saves power in transferring the output of a stage to a succeeding stage. A clocked buffer in each stage receives the propagated output from the previous stage for processing in the buffer stage. After pre-charge validation, a sequence of test patterns to the domino logic circuits occurs without testing the pre-charge circuit after each phase of the machine circuit.

Apparatus and method for simulating domino logic circuits using a

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Austin, TX, United States of America

Amy May Tuvell