International Business Machines Corporation

Amy M Youngs

Dennis G Gregoire

Ravi Kumar Arimilli

Steven Mark Thurber

Richard Louis Arndt

Edward John Silha

James O Nicholson

Yoanna Baumgartner

An interrupt subsystem within a data processing system is scalable from low-end uni-processor systems to high-end multi-processor (MP) systems. This interrupt subsystem provides for queueing of interrupts from many sources, and for queueing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software, and provides hardware independent functionality.

Scalable system interrupt structure for a multi-processing system

A system and method are provided which include devices implementing a snooping protocol. Data to be written by an I/O peripheral to an I/O controller is mapped to a specific location in memory, and then the data is actually written to an L1 cache in the controller by the I/O device. During this period when the I/O device is writing to the controller cache, the controller does not actually own the data stored in the specific memory location. Once the write operation is complete for a given memory sector, the I/O controller then performs the bus operations required to obtain ownership of the data in the specified memory location. The data read from memory is then merged with the data written from the I/O device and written back to the memory. If a snoop hit is identified by the I/O controller, during the period when the data is owned the I/O controller intervenes to prevent the memory access which caused the snoop hit. The invention limits the time period in which a snoop hit can occur to only those times when the device owning the data is already in the process of performing an atomic Read-Modify-Write operation such that reordering of queued bus transaction operations is never required.

System and method to prevent the occurrence of a snoop push during read

A system and method dynamically changes the snoop comparison granularity between a sector and a page, depending upon the state (active or inactive) of a direct memory access (DMA) I/O device which is writing to a device on the system bus asynchronously when compared to the CPU clock. By using page address granularity, erroneous snoop hits will not occur, since potentially invalid sector addresses are not used during the snoop comparison. Sector memory addresses may be in a transition state at the time when the CPU clock determines a snoop comparison is to occur, because this sector address has been requested by a device operating asynchronously with the CPU clock. Once the asynchronous device becomes inactive the system dynamically returns to a page and sector address snoop comparison granularity.

Dynamic management of snoop granularity for a coherent asynchronous DMA

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Amy M Youngs