Advanced Micro Devices Corporation

Amy M Novak

Floyd L Dankert

Alexander W Schaefer

Jerry D Moench

Grady L Giles

Joel Thornton Irby

Michael K Ciraula

Victor F Andrade

Gregory A Constant

Michael C Braganza

Randal L Posey

Soolin Kao Chrudimsky

Jan Michael Huber

An integrated circuit. The integrated circuit includes a plurality of logic circuits. The integrated circuit further includes a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for testing. The scan chain is further configured to capture data subsequent to applying the stimulus data. The integrated circuit also includes an embedded memory having a read port, wherein the read port is coupled to one or more of the plurality of logic circuits via a read path. The embedded memory includes a virtual entry having a plurality of scan-controllable storage elements. During testing, the virtual entry is operable to apply transition data to the read path in order to cause logic state transitions in the one or more logic circuits in the read path.

Apparatus for testing embedded memory read paths

A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit further includes a plurality of local bitlines, wherein each cells is coupled to one of the local bitlines. Each of the plurality of local bitlines is a differential bitline having a signal path and a complementary signal path which are cross-coupled by a pair of transistors.

Memory array with global bitline domino read/write scheme

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Austin, TX, United States of America

Amy M Novak