Intel Corporation

Hewlett-packard Development Company, L.p.

Amy L O'Donnell

George Thangadurai

Koichi Yamada

Nhon Toai Quach

Asit K Mallick

Anand Rajan

Dale Calvin Morris

Dean A Mulla

Achmed Rumi Zahir

Andrew J Fish

John V Lovelace

Suresh K Marisetty

Sham M Datta

Yan Li

Mani Ayyar

David J O'Shea

Allan Douglas Knies

Todd A Schelling

William R Greene

Bassam N Elkhoury

Craig M Valine

Donald C Soltis

Atomic sixteen-byte memory accesses are provided in a 64-bit system in which eight of the bytes are stored in a 64-bit general-purpose register and eight of the bytes are stored in a 64-bit special-purpose register. A 16-byte load instruction transfers the low eight bytes to an explicitly specified general-purpose register, while the high eight bytes are transferred to the special-purpose register. Likewise, a 16-byte store instruction transfers data from a general-purpose register and the special-purpose register. Also provided is an 8-byte compare conditioning a 16-byte exchange semaphore instruction that can be used to accelerate algorithms that use multiple processors to simultaneously read and update large databases.

Superword memory-access instructions for data processor

The present invention relates to a method and system for efficiently identifying errant processes in a computer system using an operating system (OS) error recovery method that identifies if the error caused by the errant process can be recovered and, if so, can recover from the error. The method and system of the present invention operates after standard Error Correcting Code (ECC) and parity check bit methods and systems are unsuccessful in recovering from the error. In accordance with an embodiment of the present invention, the method and system includes detecting an error during instruction execution, storing a physical address of an errant process that caused the error, and storing an execution instruction pointer (IP) in a processor including at least one critical memory structure to detect an error and a processor error processing logic hardware coupled to the at least one critical memory structure. The processor error processing logic hardware to store a physical address of an errant process that caused the error, store an execution instruction pointer (IP) in an interruption instruction pointer (IIP), determine a first virtual address from an operating system mapping table, determine a second virtual address from a translation look-aside buffer, and identify the errant process, if the physical address and the second virtual address match the physical address and the first virtual address.

Method for efficiently identifying errant processes in a computer system by the operating system (OS) for error containment and error recovery

One embodiment of the invention provides a firmware architecture which splits firmware modules to support safe updates of specific modules as well as supporting multiple different processors. A firmware image is partitioned into several different binaries based on their update requirements and processor/platform dependence. A firmware interface table enables safe updates by enabling the option of redundant copies of specific modules as well as supporting systems with different and/or multiple processor types, mixed processors from the same family, and/or fault resilient firmware updates.

Firmware architecture supporting safe updates and multiple processor types

Algorithm for non-volatile memory updates

The present invention relates to a method and system for efficiently identifying errant processes in a computer system using an operating system (OS) error recovery method that identifies if the error caused by the errant process can be recovered and, if so, can recover from the error. The method and system of the present invention operates after standard Error Correcting Code (ECC) and parity check bit methods and systems are unsuccessful in recovering from the error In accordance with an embodiment of the present invention, the method and system includes detecting an error during instruction execution, storing a physical address of an errant process that caused the error, and storing an execution instruction pointer (IP) in an interruption instruction pointer (IIP). The method further includes determining a first virtual address from an operating system mapping table, determining a second virtual address from a translation look-aside buffer, and identifying the errant process, if the physical address and the second virtual address match the physical address and the first virtual address.

An electronic system and corresponding method for verifying the integrity of code that is stored off-chip. The electronic system comprises a memory element to store Processor Abstraction Layer (PAL) code and a processor coupled to the memory element. The processor verifies the integrity of the PAL code prior to execution of the PAL code.

System and method for verification of off-chip processor code

An electronic system and corresponding method for authenticating firmware stored in a memory element external to a processor. In one embodiment, an electronic system comprises a processor and a memory element. The memory element is used to contain firmware and a digital signature of the firmware signed by a signatory. Coupled to the memory element, the processor authenticates the firmware during a predetermined condition, which occurs prior to execution of the firmware, through use of a pre-stored public key of the signatory and a pre-stored digital signature function.

System and method for authentication of off-chip processor firmware code

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Chandler, AZ, United States of America

Amy L O'Donnell