Intel Corporation

Amruthavalli Pallavi Alur

Robert L Sankman

Robert Alan May

Sri Ranga Sai Boyapati

Debendra Mallik

Wei-Lun Kane Jen

Islam A Salama

Yikang Deng

Siddharth K Alur

Sri Chaitra J Chavali

Kristof Darmawikarta

Krishna Bharath

Rahul Jain

Mitul Bharat Modi

Sheng C Li

Sai Vadlamani

Shawna M Liff

Omkar G Karhade

Rahul N Manepalli

Eng Huat Goh

Kaladhar Radhakrishnan

Kyu Oh Lee

Rajasekaran Swaminathan

Jiun Hann Sir

Vipul V Mehta

Huong T Do

Poh Boon Khoo

Ashish Dhall

Sanka Ganesan

Robert M Nickerson

Sriram Srinivasan

Sri Chaitra Jyotsna Chavali

Lilia May

Ravindranath Vithal Mahajan

Eric Jin Li

Cheng Xu

Andrew James Brown

Robert Starkston

Ji Yong Park

Lauren Ashley Link

Daniel N Sobieski

Richard Christopher Stamey

Jonathan Rosch

Scott M Mokler

Nitin A Deshpande

William J Lambert

Ram S Viswanath

Sairam Agraharam

Chong Zhang

Yongki Min

Arun Chandrasekhar

Amanda E Schuckman

Kyu-Oh Lee

Liwei Cheng

Maroun D Moussallem

Lisa Ying Ying Chen

Huong Do

Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

Ultra-thin, hyper-density semiconductor packages

An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.

Stripped redistrubution-layer fabrication for package-top embedded multi-die interconnect bridge

A microelectronics package comprises a substrate comprising at least two conductive layers that are separated by a first dielectric. At least one island comprising a magnetic material is embedded within the dielectric between the two conductive layers. An inductor structure extends within a via in the at least one island. The via extends between the two conductive layers. The inductor structure comprises a conductive wall along a sidewall of the via, and wherein the conductive wall surrounds a second dielectric and is electrically coupled to the two conductive layers.

Magnetic core inductors on package substrates

An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

Package with underfill containment barrier

Embodiments may relate to a microelectronic package that includes a substrate with a cavity therein. A component may be positioned within the substrate, and exposed by the cavity. A solder bump may be positioned within the cavity and coupled with the component, and a bridge die may be coupled with the solder bump. Other embodiments may be described or claimed.

Microelectronic package with substrate cavity for bridge-attach

A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

Microelectronic device with embedded die substrate on interposer

A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.

Package-integrated multi-turn coil embedded in a package magnetic core

Hybrid microelectronic substrates, and related devices and methods, are disclosed herein. In some embodiments, a hybrid microelectronic substrate may include a low-density microelectronic substrate having a recess at a first surface, and a high-density microelectronic substrate disposed in the recess and coupled to a bottom of the recess via solder.

Hybrid microelectronic substrates

An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.

Embedded multi-die interconnect bridge packages with lithographically formed bumps and methods of assembling same

An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

Stacked die cavity package

An apparatus is provided which comprises: a plurality of plated through holes; a material with magnetic properties adjacent to the plurality of plated through holes; and one or more conductors orthogonal to a length of the plurality of plated through holes, the one or more conductors to couple one plated through hole of the plurality with another plated through hole of the plurality such that an inductor is formed.

Via-in-via structure for high density package integrated inductor

Growing community of inventors

Tempe, AZ, United States of America

Amruthavalli Pallavi Alur