King Abdullah University of Science and Technology

Saudi Basic Industries Corporation

Amro M Elshurafa

Khaled Nabil Salama

Ahmed A Emira

Ahmed Gomaa Ahmed Radwan

Husam N Alshareef

Mahmoud N Almadhoun

Mohamed Abdelghany

Mohannad Yomn Elsayed

In accordance with the present disclosure, one embodiment of a fractal variable capacitor comprises a capacitor body in a microelectromechanical system (MEMS) structure, wherein the capacitor body has an upper first metal plate with a fractal shape separated by a vertical distance from a lower first metal plate with a complementary fractal shape; and a substrate above which the capacitor body is suspended.

Fractal structures for MEMS variable capacitors

An embodiment of a fractal fixed capacitor comprises a capacitor body in a microelectromechanical system (MEMS) structure. The capacitor body has a first plate with a fractal shape separated by a horizontal distance from a second plate with a fractal shape. The first plate and the second plate are within the same plane. Such a fractal fixed capacitor further comprises a substrate above which the capacitor body is positioned.

Fractal structures for fixed MEMS capacitors

Disclosed is a fractional order capacitor comprising a dielectric nanocomposite layer of thickness t, comprising a first side, and a second side opposite the first side, a first electrode layer coupled to the first side of the dielectric nanocomposite layer, a second electrode layer coupled to the second side of the dielectric nanocomposite layer, a complex impedance phase angle dependent on at least a material weight percentage of filler material in a dielectric nanocomposite layer.

Fractional order capacitor

Various embodiments of a high voltage charge pump are described. One embodiment is a charge pump circuit that comprises a plurality of switching stages each including a clock input, a clock input inverse, a clock output, and a clock output inverse. The circuit further comprises a plurality of pumping capacitors, wherein one or more pumping capacitors are coupled to a corresponding switching stage. The circuit also comprises a maximum selection circuit coupled to a last switching stage among the plurality of switching stages, the maximum selection circuit configured to filter noise on the output clock and the output clock inverse of the last switching stage, the maximum selection circuit further configured to generate a DC output voltage based on the output clock and the output clock inverse of the last switching stage.

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Thuwal, Saudi Arabia

Amro M Elshurafa