Texas Instruments Corporation

Amritpal Singh Mundra

Denis R Beaudoin

Mihir Narendra Mody

Charles Lance Fuoco

Kedar Satish Chitnis

Gregory Raymond Shurtz

Sriramakrishnan Govindarajan

William A Mills

Timothy David Anderson

Kai Chirca

Gary A Cooper

Jason Lynn Peck

Jose Luis Flores

Chunhua Hu

William Cronin Wallace

Brian Jason Karguth

Anthony J Lell

Yashwant Dutt

Madan Srinivas

Robert John Tivy

Sachin Billore

Kavitha Malarvizhi

Eric Lasmana

Rajasekhar Reddy Allu

Prasanth Viswanathan Pillai

Erkan Bilhan

Maneesh Soni

Prithvi Shankar Yeyyadi Anantha

David Peter Foley

Santhanakrishnan Badri Narayanan

Rajitha Padakanti

Thomas H McKinney

Jagdish Doma

Jagdish Shantiban Housing Soc Doma

Methods, apparatus, systems, and articles of manufacture are described corresponding to immutable configuration of memory devices. An example memory includes a memory bank including a first portion and a second portion, the second portion configured to store configuration information that specifies whether the first portion is immutable; and a controller coupled to the memory bank, the controller configured to determine whether to prevent data from being written to the first portion based on the configuration information.

Methods and apparatus to facilitate immutable configuration of memory devices

This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.

Safe, secure, virtualized, domain specific hardware accelerator

Devices, systems and techniques for implementing freedom from interference (FFI) access rules. In an example, a device includes a set of primary components, a set of secondary components, and an interconnected coupled between the two sets of components. Each primary component of the set of primary components has an access identifier, among multiple access attributes, and an access attribute, among multiple access modes. Each secondary component of the set of secondary components is protected by a firewall. Each firewall is configured to specify, for each specific combination of an access identifier and access attribute, whether access to the associated secondary component is permitted and what type of access is permitted.

Method and system for freedom from interference (FFI)

A real time, on-the-fly data encryption system is operable to encrypt and decrypt data flow between a secure processor and an unsecure external memory system. Multiple memory segments are supported, each with its own separate encryption capability, or no encryption at all. Data integrity is ensured by hardware protection from code attempting to access data across memory segment boundaries. Protection is also provided against dictionary attacks by monitoring multiple access attempts to the same memory location.

Hardware protection of inline cryptographic processor

Circuits, systems and methods are provided. A circuit includes a subsystem, an interface, and a debugger. The interface includes power processing and management (PPM) circuitry coupled to the subsystem, and arbitration logic coupled to the PPM circuitry. In operation, the debugger issues a debug request to the arbitration logic to perform a debug operation on the subsystem, and, in response to the debug request, the arbitration logic provides an interrupt associated with the subsystem to the PPM circuitry. The PPM circuitry, in response to the interrupt and a determination that the subsystem is OFF, powers on the subsystem and provides a notification to the arbitration logic indicating that the subsystem is ON. The PPM circuitry also receives a notification from the arbitration logic that the debug operation related to the debug request is complete, and powers off the subsystem in response to that notification.

Integrated circuit with debugger and arbitration interface

In described examples, a system on a chip (SoC) and method for sending messages in the SoC include determining locations of initiator-side firewall block and receiver-side firewall block memories using respective pointers to the firewall block memories stored in a single, contiguous memory. Addresses of the pointers within the single memory depend on respective unique firewall identifiers of the firewall blocks. An exclusive security configuration controller uses the pointers to configure the firewall blocks over a security bus which is electrically isolated from a system bus. The system bus is used to send messages from sending functional blocks to receiving functional blocks. The initiator-side firewall block adds a message identifier to messages. The message identifier depends on the initiator-side firewall block's configuration settings. The receiver-side firewall block controls permission for the receiving functional block to access the message, depending on the message identifier and the receiver-side firewall block's configuration settings.

System on chip firewall memory architecture

A system-on-chip (SoC) is provided that includes security control registers, the security control registers including security flags for security critical assets of the SoC, wherein each security flag includes multiple bits.

Hardware countermeasures in a fault tolerant security architecture

A method of enabling memory access freedom from interference (FFI) rules, comprising: determining a first safety privilege access ID (PrivID) for a first component of a system (e.g., based on Automotive Safety Integrity Level (ASIL) attributes of tasks executed by the first component); determining a first access attribute for a first software task executing on the first component; receiving, at a first firewall component of the system, a request from the first software task to access a first memory region of a second component of the system, wherein the request specifies the first PrivID and the first access attribute; and determining, by the first firewall component, whether to permit the first software task to access the first memory region based on the first PrivID, the first access attribute, and the first memory region.

In described examples, a method of routing messages in a system on a chip (SoC) includes a secure message router receiving a message including a content, an identifier of the message's sending (origin) functional block and/or of a receiving (destination) functional block, a message secure value, a promote value, and a demote value. A context corresponding to the identifier is retrieved from a memory. The context includes an allow promote value and an allow demote value. The message secure value is increased if the promote value requests the increase and matches the allow promote value. The message secure value is decreased if the demote value requests the decrease and matches the allow demote value. Cleartext corresponding to the content is made accessible by the destination if the context secure value matches the message secure value. The message is then outputted from the secure message router to the destination.

Secure message routing

An integrated circuit includes: a debugger; and an interface coupled to the debugger. The interface has: arbitration logic coupled to the debugger; a power processor coupled to the arbitration logic; and a power management network coupled to the power processor. The integrated circuit also includes subsystems coupled to the interface. The debugger is configured to perform debugging operations of the subsystems via the interface.

A real time, on-the-fly data encryption system is shown operable to encrypt and decrypt the data flow between a secure processor and an unsecure external memory system. Multiple memory segments are supported, each with its own separate encryption capability, or no encryption at all. Data integrity is ensured by hardware protection from code attempting to access data across memory segment boundaries. Protection is also provided against dictionary attacks by monitoring multiple access attempts to the same memory location.

An embedded device is provided that is configured to randomize execution time of a boot process of the embedded device performed responsive to a reset signal, wherein reset release time is nondeterministic. The embedded device may include a randomizer component configured to generate a timeout signal after a random interval, wherein to randomize execution time, the embedded device is further configured to execute a first portion of a reset process, signal the randomizer component to generate the timeout signal after a first random interval, wait for the timeout signal, and execute a second portion of the reset process responsive to the timeout signal.

Randomized execution countermeasures against fault injection attacks during boot of an embedded device

A flexible hybrid firewall architecture is disclosed. A system implementing such an architecture includes an access control register, a memory having at least a region to which access is controllable by the access control register, the access control register including first field that contains a privilege identifier (ID) and a plurality of additional fields, each additional field containing control bits corresponding to a respective one of a plurality of permission levels, and control circuitry that, in response to receiving a transaction containing a transaction privilege ID, a security indicator, and a privilege indicator, controls access to the region when the transaction privilege ID matches the privilege ID contained in the first field by using the control bits of a field of the additional fields that corresponds to a security level indicated by the security indicator and a privilege level indicated by the privilege indicator of the transaction.

Flexible hybrid firewall architecture

A financial transaction system includes sensors, a tamper detection module, and circuitry configurable to control which sensors are used, and the circuitry is configurable after the tamper detection module has been manufactured.

Growing community of inventors

Dallas, TX, United States of America

Amritpal Singh Mundra