Freescale Semiconductor,inc.

Nxp Usa, Inc.

Amrit Pal Singh

Arvind Kaushik

Peter Zahariev Rashev

Akshat Mittal

Puneet Khandelwal

Nitin Vig

Arnab K Mitra

Somvir Dahiya

Girraj K Agrawal

Mohit K Prasad

Gaurav Davra

Vincent Pierre Martinez

Rahul Garg

Joseph Gergen

Asif Iqbal

Ankit Pal

Nikhil Jain

Mohit Gupta

Pradeep Singh

Kaushik Arvind

Aviel Livay

Ritika Sharma

First and second processors that are in communication with each other are disclosed. The first processor includes a sampling controller, a sampling circuit, and a data flow controller. The sampling controller is configured to receive multiple identifiers and corresponding enable signals associated with data that is to be transmitted to or received from the second processor, and generate an identification signal and a sampling signal based on one of the identifiers and the corresponding enable signal. The sampling circuit is configured to sample multiple data counts to generate corresponding sampled counts based on the identification signal and the sampling signal. The data flow controller is configured to generate a control signal based on the identifiers, the corresponding enable signals, the data counts, and the corresponding sampled counts to control data flow between the first and second processors.

System for controlling data flow between multiple processors

A transaction controller orders transactions between a master device and a slave device, where the transactions may be received out-of-order. First and second transactions have respective first and second sets of data packets. The transaction controller includes a transaction table, a first ordering counter, and a first sequence counter having first and second values when the first and second transactions are initiated. The first and second values are stored in the transaction table based on first and second transaction identifiers (TIDs) that are associated with the first and second transactions. The transaction controller determines, based on the second value, the second TID, and a current value of the first ordering counter, whether the first and second sets of data packets were received out-of-order. Based on the determination, the second set of data packets is transmitted to the master device after the first set of data packets.

Controller for ordering out-of-order transactions in SoC

In at least one embodiment, a method for handling data units in a multi-user system includes granting a shared resource to a user of a plurality of users for a transaction associated with an entry of a transaction data structure. The method includes determining whether the transaction stored last partial data of a data unit associated with the user in an alignment register associated with the user. The method includes asserting a request for arbitration of a plurality of transactions associated with the plurality of users. The request is asserted for an additional transaction associated with the entry in response to determining that the transaction stored the last partial data in the alignment register. The method may include flushing the last partial data from the alignment register to a target memory in response to detecting an additional grant of the shared resource to the user for the additional transaction.

Protocol data unit end handling with fractional data alignment and arbitration fairness

Systems and related methods are disclosed to manage memory for an integrated circuit including a processor and logic circuitry to manage the memory. The memory includes segments available for storage of data, and the processor stores data within the memory. Logic circuitry is configured to manage the memory, forms a plurality of sections within the segments, and applies tokens to the plurality of sections. Further, for each storage operation, the logic circuitry searches the tokens to identify blocks of continuous available tokens based upon data length, selects a block from the blocks identified in the search, determines a first token for the selected block, and outputs a memory address to the processor based upon the first token. The processor stores the data at the memory address. For one embodiment, the storage operations are associated with storage of data within packets received from network communications.

Hardware-based memory management for system-on-chip (SoC) integrated circuits that identify blocks of continuous available tokens needed to store data

An apparatus for reception and detection of RACH data in an LTE input signal includes a hardware accelerator that has a decimator that filters and down-samples the input signal, a first Fourier transform circuit that transforms the decimated signal from the time domain to the frequency domain, and a second transform circuit that multiplies the resulting signal by a complex Z-C sequence and performs an inverse Fourier transform (iFT) operation to transform the multiplied signal from the frequency domain to the time domain. A DSP performs a delay profile analysis operation on the signal resulting from the iFT operation.

Apparatus for reception and detection of random access channel (RACH) data

An eNode-B includes PUSH mapping hardware for improved performance. A scheduler schedules first and second code words of first and second respective user devices. A buffer receives and stores first and second identifiers. A de-multiplexer outputs a first code word number based on the first identifier and a second code word number based on the second identifier. A set of completion queues store the first and second code word numbers. A sequence controller generates first and second select signals corresponding to the first and second identifiers. A multiplexer outputs one of the first and second code word numbers based on the select signals, and the scheduler schedules the first and second code words based on the first and second identifiers.

Scheduler for layer mapped code words

A FIR filter includes segment cells, each of which is configurable as an interpolation filter, a decimation filter, a symmetric filter, or an asymmetric filter. Two or more of the segment cells are configurable to be cascaded to form an interpolation filter, a decimation filter, a symmetric filter, an asymmetric filter, a complex symmetric filter, or a complex asymmetric filter. The FIR filter includes registers corresponding to the segment cells for storing coefficient values of the corresponding segment cells. The FIR filter further includes control circuits corresponding to the segment cells for generating control signals.

Configurable FIR filter with segmented cells

A system for mapping control and user data includes a direction scanner, an address calculator, a collision detector, a buffer, and a mapper for mapping control and user data from a first memory to a second memory. The direction scanner determines the highest priority value of to a code word index. The address calculator calculates start and end addresses of the highest priority value. When an address from an address range, defined by the start and end addresses, is already mapped to other control data, the collision detector detects a collision and generates feedback data. The address calculator outputs modified start and end addresses based on the feedback data. When no collision is detected, the address calculator outputs the modified start and end addresses to the buffer. The mapper then maps the control and user data to the modified start and end addresses in the second memory.

System and method for mapping control and user data

A system for storing pre-distorted output samples in a memory includes a sample counter, a programming interface module, and a comparator. The sample counter counts the pre-distorted output samples, generates a dynamic count value, receives a capture counter status signal, and generates a first count value. The programming interface module receives and outputs the first count value, an offset value, and a capture control signal, and generates a first interrupt signal. The comparator receives the first count value, the offset value, the dynamic count value, and the capture control signal, generates a final value, compares the final value with the dynamic count value, and generates a trigger signal when the final value equals the dynamic count value based on the capture control signal. The trigger signal initiates the storing of the pre-distorted output samples in the memory.

Synchronous bus architecture for digital pre-distortion system

A system for calibrating a power amplifier (PA) includes a memory, a processor, a digital pre-distorter (DPD), and a data converter. The DPD includes a programming interface module, a pattern generator, a multiplier, and a pre-distorter module. The multiplier multiplies reference baseband stream data from the memory with pattern coefficient data generated by the pattern generator to generate shaped reference baseband stream data. The pre-distorter module generates pre-distorted shaped reference baseband stream data. The PA receives a low-power reference radio frequency (RF) signal corresponding to the pre-distorted shaped reference baseband stream data and generates a high-power reference RF signal. The processor receives and compares the pre-distorted shaped reference baseband stream data with amplified shaped reference baseband stream data corresponding to the high-power reference RF signal, and adjusts pre-distortion parameters in the pre-distorter module based on the comparison such that the PA generates a linear high-power RF signal.

System for calibrating power amplifier

A digital pre-distorter (DPD) for an RF transceiver system having multiple antennas includes a DPD controller, first and second address generators, stream select and antenna select muxes, first and second lookup tables (LUTs), first and second dynamic routing logic units, multipliers, an adder, and an accumulator. The DPD controller generates antenna select, stream select and stream routing signals indicative of selection of antennas, the first and second LUTs, and input signals. The DPD controller configures the DPD to share the multipliers and the first and second LUTs between multiple antennas by providing the antenna select signal to the antenna select mux, the stream select signal to the stream select mux, and the stream routing signals to the first and second dynamic routing logic units.

Digital pre-distorter

A system for reducing in-phase and quadrature-phase (I/Q) impairments includes first, second, third, and fourth programmable registers for storing respective first, second, third, and fourth values, first and second finite impulse response (FIR) filters having respective first and second sets of filter taps, and first and second adders. The first FIR filter receives an I input signal and generates first and second intermediate output signals based on the first and second values for I and Q channels, respectively. The second FIR filter receives a Q input signal and generates third and fourth intermediate output signals based on the third and fourth values for the I and Q channels, respectively. The first and second adders receive the first and second, and the third and fourth intermediate output signals, respectively, and generate compensated I and Q output signals for the I and Q channels.

System for compensating for I/Q impairments in wireless communication system

A channel equalizer that compensates for signal distortion of a signal in a communication channel includes an equalization filter, which gain-equalizes a received signal received through the communication channel, and an equalization control circuit, which generates a gain control signal for controlling the gain of the equalization filter. The equalization control circuit specifies a phase switch in data obtained by the equalization filter as an isolated bit and generates the gain control signal based on a width of the isolated bit.

Digital adaptive channel equalizer

A system and method for reducing power consumption in a Low Density Parity-Check Code (LDPC) decoder includes a sleep mode checking module and a gating circuit. The sleep mode checking module checks whether a check node is in sleep mode. The check node is considered to be in sleep mode when the absolute value of the message going to each of the one or more bit nodes corresponding to the check node is greater than a threshold value. The gating circuit turns OFF a Check Node and Bit Node Update Unit (CNBNU) associated with the check node when the check node is in the sleep mode. Turning OFF a CNBNU stops the exchange of messages between the check node and its corresponding one or more bit nodes.

System and method for reducing power consumption in a low-density parity-check (LDPC) decoder

A clock generation circuit for an integrated circuit device, such as an SOC, has increased test coverage. The clock generation circuit includes first and second latches that receive an input clock signal at their clock inputs and a selector that receives at first and second data inputs respectively, the input clock signal and an output of the second latch circuit, which is a divided clock signal. A logic gate has a first input connected to an output of the first latch and a second input that receives a scan mode signal. The logic gate generates a selector control signal provided to the selector.

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Ludhiana, India

Amrit Pal Singh