Tower Semiconductor Ltd.

Technion Research & Development Foundation Limited

Hillberry Gat Ltd.

Amos Fenigstein

Yakov Roizin

Assaf Lahav

Avi Strum

Alexey Heiman

Tomer Leitner

Raz Reshef

Michael Lisiansky

Ira Naot

Shay Alfassi

Guy Yehudian

Doron Pardess

Zohar Kuritsky

Hai Reznik

Doron Amihood

David Cohen

Yael Nemirovsky

Evgeny Pikhay

Efraim Aloni

Igor Brouk

Alexei Heiman

Sharon Bar-Lev Shefi

David Avner

Vitali Savuskan

Myriam Buchbinder

Viktor Goldovsky

Yohanan Davidovich

Dmitry Dain

Gil Visokolov

Hironori Matsuyoshi

Toshiaki Ohmi

David Choen

Asaf Lahav

There may be provided a radiation sensor, that may include multiple semiconductor regions that form a sensing PN junction and a draining PN junction that is located below the sensing PN junction; a bias circuit that is configured to (i) bias the sensing PN junction to maintain a sensing PN junction depletion region of a fixed size during a first sensing period and during a second sensing period, and (i) bias the draining PN junction to form a draining PN junction depletion region of a first size during the first sensing period and of a second size during the second sensing period; and an output circuit that is configured to generate a first output signal that represent sensed radiation out of radiation that impinged on the radiation sensor during the first sensing period, and to generate a second output signal that represent sensed radiation out of radiation impinged on the radiation sensor during the second sensing period.

Wavelength selective radiation sensor

A sensor circuit having a Single Photon Avalanche Diode (SPAD) and an active quenching circuit including a quenching transistor controlled by a one-shot (or similar) circuit is disclosed. The quenching transistor applies a reverse-bias voltage level on the cathode of the SPAD. During photon detection events, pulses generated by the SPAD's avalanche breakdown trigger the one-shot circuit to de-actuate the quenching transistor, allowing the cathode potential to drop below the SPAD's breakdown voltage. After a delay period, which is defined by the one-shot's configuration, allows reliable completion of the avalanche breakdown process, the one-shot circuit re-actuates the quenching transistor such that the SPAD's cathode is refreshed to the reverse-bias voltage level. The one-shot circuit is optionally coupled by way of capacitors to the SPAD and the quenching transistor to facilitate implementation using standard CMOS elements. The sensor is suitable for use in a LIDAR system.

Active quenching for single-photon avalanche diode using one- shot circuit

A system that may include (a) a radiation source that is constructed and arranged to illuminate an object with radiation during consecutive time frames of microsecond-scale duration, wherein radiation emitted during one time frame differs by energy from radiation transmitted during an adjacent time frame; and (b) a CMOS sensor that may include a readout circuit and CMOS pixels. Each CMOS pixel may include a radiation sensing element and in-pixel memory elements. Different in-pixel memory elements are constructed and arranged to sample a state of the radiation sensing element during different time frames of the consecutive time frames.

Image sensor module and a method for sensing

An image sensor module that comprises a die, wherein the die comprises light sensors and optics; and wherein the optics comprises luminescent elements that represent die manufacturing information that is indicative of a manufacturing process of the die.

Image sensor module and a method for evaluating an image sensor

A Schmitt trigger's hysteresis is established by standard and non-standard MOSFETs having different (lower/higher) threshold voltages. For example, a standard n-channel transistor having a relatively low threshold voltage (e.g., 1V) sets the lower trigger switching voltage, and a non-standard n-channel transistor (e.g., an n-channel source/drain and a polysilicon gate doped with a p-type dopant) exhibits a relatively high threshold voltage (e.g., 2V) that sets the higher trigger switching voltage. An output control circuit generates the Schmitt trigger's digital output signal based on the on/off states of the two (non-standard and standard) MOSFETs, whereby the changes digital output signal between two values when the analog input signal falls below the lower threshold voltage (i.e., when both MOSFETs are turned on/off) and rises above the higher threshold voltage (i.e., when both MOSFETs are turned off/on). Self-resetting and other circuits utilize the Schmitt trigger to facilitate, e.g., high dynamic range image sensor pixels.

Schmitt trigger circuit with hysteresis determined by modified polysilicon gate dopants

A backside illuminated semiconductor image sensor that includes a Fabry-Perot resonator tuned to absorb near infrared (NIR) radiation; wherein the Fabry-Perot resonator comprises a front reflector, a back reflector and an active Silicon layer between the front reflector and the back reflector.

Backside illuminated (BSI) CMOS image sensor (CIS) with a resonant cavity and a method for manufacturing the BSI CIS

A global shutter image sensor formed on an n-type bulk substrate and including pixels having pinned n-type photodiodes and memory nodes formed in designated n-doped epitaxial layer regions that are separated from the bulk substrate by a p-type vertical (potential) barrier implant. Each memory node includes both a buried channel portion and a contiguous pinned diode portion having different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion during global charge transfer from an adjacent photodiode. The p-type vertical (potential) barrier implant is coupled to ground, and the bulk substrate is switched between a low integration voltage level during integration periods, and a high reset voltage level, whereby the photodiodes are globally reset without requiring reset transistors. P-type sinker implant sections and p-type vertical barrier implants form box-like diffusions around each pixel's photodiode and memory node.

Image sensor pixel with memory node having buried channel and diode portions formed on N-type substrate

A method for manufacturing a metal insulator metal (MIM) trench capacitor, the method may include forming a cavity in an Intermetal Dielectric stack, wherein a bottom of the cavity exposes a lower metal layer; wherein the Intermetal Dielectric stack comprises a top dielectric layer; depositing a first metal layer on a bottom of a cavity and on sidewalls of the cavity; depositing a sacrificial layer over the first metal layer; filling the cavity with a filling material; removing, by a planarization process, a portion of the sacrificial layer positioned above the top dielectric layer and a portion of the first metal layer positioned above the top dielectric layer to expose an upper portion of the sacrificial layer and an upper portion of the first metal layer; forming a recess by removing the upper portion of the sacrificial layer and the upper portion the first metal layer while using the filling material as a mask; removing the filling material by a first removal process that is selective to the sacrificial layer and to the first metal layer; removing the sacrificial layer by a second removal process that is less aggressive than the first removal process; fabricating an insulator layer on the first metal layer; and depositing a second metal layer on the insulator layer.

Method for manufacturing a trench metal insulator metal capacitor

A global shutter (GS) image sensor pixel includes a pinned photodiode connected to a memory node by a first transfer gate transistor, and a floating diffusion connected to the memory node by a second transfer gate transistor. The memory node includes a buried channel portion disposed under the first transfer gate transistor and a contiguous pinned diode portion disposed between the first and second transfer gate transistors, where the two memory node portions have different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion. The floating diffusion node similarly includes a buried channel portion disposed under the second transfer gate transistor and a contiguous pinned diode portion that generate a second intrinsic lateral electrical field that drives electrons into the pinned diode portion of the floating diffusion. A 6T CMOS pixel is disclosed that facilitates low-noise CDS readout.

Image sensor pixel with memory node having buried channel and diode portions

A single-exposure high dynamic range (HDR) image sensor utilizes a charge amplifier having a selectively coupled conversion capacitor to read a single photodiode charge during a multi-phase readout operation. An overflow readout is performed during the photodiode charge integration phase, and utilizes the conversion capacitor to read overflow signals indicating rapidly rising photodiode charges caused by extreme exposure conditions, which also prevents saturation of the photodiode. At the end of the integration phase, the remaining photodiode charge is then measured using two readouts: a high sensitivity readout during which the storage capacitor de-coupled to accurately measure low-light conditions, and a low sensitivity readout during which the remaining photodiode charge is stored on the storage capacitor to provide normal light image data. Final single exposure HDR image data is then calculated by summing the overflow image data with the high-sensitivity and/or the low-sensitivity image data.

Single-exposure high dynamic range CMOS image sensor pixel with internal charge amplifier

A method for fabricating image sensors and other semiconductor ICs that controls the amount of hydrogen generated during back-end processing. The back-end processing includes forming multiple metallization layers after front-end processing is completed (i.e., after forming the pre-metal dielectric), where each metallization layer includes a patterned aluminum structure, an interlevel dielectric (ILD) layer including TEOS-based oxide formed over the patterned aluminum structure. A cap layer including a low-moisture content oxide such as silane oxide (i.e., SiOgenerated by way of a silane CVD process) is formed over at least one ILD layer. The cap layer serves as an etch-stop for the subsequently-formed metal layer of a next metallization layer by isolating the underlying ILD material from the plasma environment during aluminum over-etch, which significantly reduces the production and migration of hydrogen into front-end structures.

Back-end processing using low-moisture content oxide cap layer

Some demonstrative embodiments include devices and/or methods of Back Side Illumination (BSI) Complementary Metal-Oxide-Semiconductor (CMOS) pixel array. For example, a BSI CMOS pixel array may include a plurality of pixels, a pixel of the plurality of pixels may include one or more Metal-Oxide-Semiconductor (MOS) transistors comprising one or more well regions, a well region of the one or more well regions comprising an N-Well (NW) region or a P-well (PW) region; a photodiode; an epitaxial (epi) layer comprising an absorption area and a collection area, the absorption area to absorb incoming photons and to generate electrons responsive to absorbed photons, and the collection area connecting the absorption area to the photodiode to provide the electrons from the absorption area to the photodiode; and a barrier layer separating the absorption area from the one or more well regions.

Apparatus, system and method of back side illumination (BSI) complementary metal-oxide-semiconductor (CMOS) pixel array

A method for operating a global shutter image sensor includes performing both a global shutter (image capture) operation and a rolling shutter (readout) operation. During the global shutter operation, image information (charges) are captured by photodiodes in every pixel, and then simultaneously transferred to charge coupled gate (CCG) devices provided in each pixel. The rolling shutter operation includes performing multiple correlated double sampling (CDS) readout phases utilizing readout circuits that are shared by groups of pixels (e.g., four pixels share each readout circuit) having CCG devices connected in a chain. After resetting a floating diffusion in the readout circuit, a first captured charge is transferred to floating diffusion for readout, and the remaining charges are shifted along the CCG chain. The remaining CCG devices are then sequentially read out by repeating the read-and-shift operation. The readout operation is then repeated for each row of pixel groups.

Shared readout low noise global shutter image sensor method

A global shutter image sensor includes an array of pixel groups arranged in rows and columns, each pixel group including four pixels and a shared readout circuit having a floating diffusion. Each pixel includes a photodiode, a transfer gate and a charge coupled gate (CCG) device. The CCG devices are coupled in series with the floating diffusion of the shared readout circuit. Control circuitry controls the image sensor such that all of the pixels simultaneously capture image information (charges) and then transfer the captured charges to the CCG devices during a global shutter operation. The control circuit then controls the CCG devices to act as a shift register that transfers the captured charges to the floating diffusion during sequential correlated double sampling readout phases. The readout circuit includes a shared reset transistor, a source-follower and row select transistor, and each pixel group is controlled by eight or fewer control signals.

Shared readout low noise global shutter image sensor

A single-exposure high dynamic range (HDR) image sensor utilizes a charge amplifier having two different charge-to-voltage conversion capacitors that read a single photodiode charge during a two-phase readout operation. The first capacitor has a lower capacitance and therefore higher conversion gain (sensitivity), and the second capacitor has a higher capacitance and therefore lower conversion gain (sensitivity). The two-phase readout operation samples the photodiode charge twice, once using the high sensitivity capacitor and once using the low sensitivity capacitor. The high sensitivity readout phase provides detailed low light condition data but is saturated under brighter light conditions, and the low sensitivity readout phase provides weak data under low light conditions but provides high quality image data under brighter light conditions. The final HDR image is created by combining both high and low sensitivity images into a single image while giving each of them the correct weighted value.

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Haifa, Israel

Amos Fenigstein