National Semiconductor Corporation

Amolak R Ramde

Sheldon Aronowitz

Surinder Krishna

Wadie N Khadder

A process is disclosed for controlling the diffusion of aluminum in silicon for the fabrication of monolithic pn junction isolated integrated circuits. Germanium is incorporated into the silicon where isolation or p-well diffusion of aluminum is to occur. Aluminum diffusion is modified by the presence of the germanium so that channeling and out diffusion are controlled. The control is enhanced when boron is incorporated into the silicon along with the aluminum.

Control and moderation of aluminum in silicon using germanium and

A process for creating self-aligned vertically arrayed planar transistors. The preferred embodiment relates to the simultaneous fabrication of both NPN and PNP planar vertically arrayed transistors in a conventional monolithic, epitaxial, PN junction isolated, integrated circuit. A field oxide is employed to surface isolate the devices and assist in the self-alignment improvement.

Self-aligned planar monolithic integrated circuit vertical transistor

A P-type buried layer is described for use with planar, silicon, monolithic, epitaxial, PN junction-isolated transistors of PNP conductivity primarily for use in IC construction. The buried layer includes a high concentration of boron and gallium along with germanium, which is in sufficient concentration to inhibit impurity diffusion in the silicon epitaxial layer. This inhibition effect has been found to be sufficient to cause the combination of boron and gallium to act as slow diffusers. The result is that the performance of arsenic and antimony, in the creation of buried layers for NPN transistors. Thus, the performance of NPN transistors can be matched for PNP transistors. This means that an IC can be fabricated so that more nearly equal performance NPN and PNP transistors can be fabricated simultaneously in a common substrate.

Method of fabricating P-buried layers for PNP devices

In a monolithic silicon integrated circuit fast diffusing impurities are incorporated into the collectors of the bipolar lateral transistors. The impurity level is controlled, using ion implantation, so that after device processing the lateral transistor collectors extend an additional increment into the base. This increment is doped with the fast diffusing impurity at a level that overcompensates the normal base impurity to the opposite conductivity type and conductivity about equal to that of the base. Thus the collector junction is moved towards the emitter and is symmetrical in terms of conductivity. This means that when the collector is reverse biased the depletion field extends about equally on both sides of the junction. This action greatly relieves the voltage gradient and stress so that collector junction voltage breakdown is enhanced. Since the collector junction is closer to the emitter the transistor current gain and frequency response are enhanced.

Integrated circuit lateral transistor structure

A semiconductor substrate having an epitaxial layer on its upper surface is provided with a masking layer. Holes are photolithographically etched in the masking layer where isolation diffusion regions are to be formed. Then aluminum ions are implanted into the surface and diffused completely through the epitaxial layer so as to create tubs of epitaxial material that are PN junction isolated. Since aluminum is a fast diffuser, the diffusion time is greatly reduced, thereby reducing the up diffusion of buried N+ collector so that the original epitaxial layer can be made relatively thin. Lateral isolation diffusion is reduced, thereby substantially reducing the surface area required for isolation. Thus, the process is capable of increasing the component density in the completed integrated circuit.

Growing community of inventors

San Jose, CA, United States of America

Amolak R Ramde