Spansion Llc.

Advanced Micro Devices Corporation

Intermolecular, Inc.

Globalfoundries Inc.

Cypress Semiconductor Corporation

Intel Corporation

Infineon Technologies LLC

Monterey Research, LLC

Amol Ramesh Joshi

Kuo-Tung Chang

Meng Ding

Minh Van Ngo

Angela Tai Hui

Shenqing Fang

Hidehiko Shiraiwa

Youseok Suh

Wenmei Li

Hiroyuki Kinoshita

Olov B Karlsson

Chih-Yuh Yang

Chungho Lee

Zhendong Hong

David H Matsumoto

Usha Raghuram

Lovejeet Singh

Ning Cheng

Harpreet Kaur Sachar

Tim Thurgate

Salil Mujumdar

Paul Raymond Besser

Hoon Sik Kim

Kisik Choi

Jinping Liu

Chi K Chang

Takashi Whitney Orimoto

John S Foster

Lei Xue

Ashot Melik-Martirosian

Ashish Bodke

Minghao Shen

Kyunghoon Min

Bei Li

Divya Pisharoty

Susie Tzeng

Hapreet Sachar

Bin Yang

Krishna Kumar Parat

Dipankar Pramanik

Yu Nan Sun

Scott Allan Bell

Chi-I Lang

Richard M Fastow

Mark W Randolph

Darlene G Hamilton

Yi He

Zhizheng Liu

Ankur Agarwal

Rinji Sugino

Frank Greer

Mark V Raymond

Satoshi Torii

Allison Holbrook

Yukio Hayakawa

Jayendra D Bhakta

Kevin Kashefi

Sung-Yong Chung

Hiroyuki Nansei

Gulzar Ahmed Kathawala

Edward Franklin Runnion

Albert Sanghyup Lee

Xuehong Yu

Sandip Niyogi

Narayanan Ramanan

Sung-Chul Lee

Charlene Chen

Jingang Su

J Watanabe

Xin Sun

Takayuki Maruyama

Wei Cao

Abhijit Pethe

Hyungseok Kim

Norimitsu Takagi

Yuji Mizuguchi

Yanxia (Emma) Lin

Xianmin Yi

Yanxiang Liu

In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.

Contacts for semiconductor devices

An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.

Method and apparatus to mitigate hot electron read disturbs in 3D NAND devices

A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

System and method for manufacturing self-aligned STI with single poly

A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.

An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.

Gate structures for transistor devices for CMOS applications and products

Native oxide growth on germanium, silicon germanium, and InGaAs undesirably affects CET (capacitive equivalent thickness) and EOT (effective oxide thickness) of high-k and low-k metal-oxide layers formed on these semiconductors. Even if pre-existing native oxide is initially removed from the bare semiconductor surface, some metal oxide layers are oxygen-permeable in thicknesses below about 25 &#x212b; thick. Oxygen-containing species used in the metal-oxide deposition process may diffuse through these permeable layers, react with the underlying semiconductor, and re-grow the native oxide. To eliminate or mitigate this re-growth, the substrate is exposed to a gas or plasma reductant (e.g., containing hydrogen). The reductant diffuses through the permeable layers to react with the re-grown native oxide, detaching the oxygen and leaving the un-oxidized semiconductor. The reduction product(s) resulting from the reaction may then be removed from the substrate (e.g., driven off by heat).

Reduction of native oxides by annealing in reducing gas or plasma

Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The remote plasma source may be used to provide a plasma surface treatment or as a source to incorporate dopants into a pre-deposited layer.

Method to control depth profiles of dopants using a remote plasma source

One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

Methods of forming gate structures for transistor devices for CMOS applications

Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.

Circular transmission line methods compatible with combinatorial processing of semiconductors

Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.

High productivity combinatorial oxide terracing and PVD/ALD metal deposition combined with lithography for gate work function extraction

A method of processing a substrate is provided. The method includes forming a first oxide layer on the substrate and patterning the first oxide layer utilizing a lithography process, the patterning defining a plurality of active areas on the substrate. The method includes forming a second oxide layer in each active area and forming a plurality of metal electrodes over the second oxide layer through a shadow mask technique, wherein the shadow mask technique is performed without alignment to an active area.

Method for forming MOS capacitor

Self-aligned STI with single poly for manufacturing a flash memory device

A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.

Memory cell system with charge trap

Growing community of inventors

Sunnyvale, CA, United States of America

Amol Ramesh Joshi