International Business Machines Corporation

Globalfoundries Inc.

Amol Anil Joshi

Peter Anton Habitz

William John Wright

John E Barwin, Iii

Robert J Gauthier, Jr

Baozhen Li

Michael Richard Ouellette

JunJun Li

Eric A Foreman

Vladimir P Zolotov

Jeffrey G Hemmett

Natesan Venkateswaran

Amith Singhee

Paul Steven Zuchowski

Jerry D Hayes

Bradford Lawrence Hunter

Leon Jacob Sigal

John P Dubuque

Wangyang Zhang

Brian A Worth

William John Livingstone

Faraydon Pakbaz

Sanjay Upreti

Kurt A Carlsen

James E Sundquist

Gregory J Schroer

David Bruce White

Jason Chung

Nilesh C Date

Christopher J Kiegle

A method is disclosed comprising using a circuit recognition engine running on a computerized device to detect a number and type of devices in an integrated circuit. The method characterizes device variation by selecting a set of dominant active devices and performing simulation using the set of dominant active devices. Three different options may be used to optimize the number of simulations for any arc/slew/load combination. Aggressive reduction uses a minimal number of simulations at the cost of some accuracy loss, conservative reduction reduces the number of simulations with negligible accuracy loss, and dynamic reduction dynamically determines the minimum number of simulations needed for a given accuracy requirement.

Dynamically determining number of simulations required for characterizing intra-circuit incongruent variations

A method of characterizing an electromigration (EM) parameter for use in an integrated circuit (IC) chip design including, inputting a layout of a wire layer and identifying a signal gate-circuit including electrically parallel paths, connected to an output of the signal gate from the layout. Based on widths for each of the paths, determining a maximum possible current for each of the paths, and calculating an average current for each of the paths. Identifying a path that is most limited in its current carrying capacity by possible EM failure mechanisms, and storing in a design library, a possible maximum current output to the identified limiting path, as the EM parameter.

Identifying and mitigating electromigration failures in signal nets of an integrated circuit chip design

Methods and systems perform a simulation on an integrated circuit design by applying a first value to a first variable and a second value to a second variable of the simulation to produce a first matrix corner simulation value. The methods and systems repeat the simulation using different values for the first and said second variables to produce a second matrix corner simulation value, a third matrix corner simulation value, and a fourth matrix corner simulation value. The methods and systems create a matrix, and the matrix has the first matrix corner simulation value, the second matrix corner simulation value, the third matrix corner simulation value, and the fourth matrix corner simulation value. The methods and systems interpolate all remaining values within the matrix based upon existing simulation values within the matrix.

Integrated circuit design simulation matrix interpolation

Methods and systems for determining timing constraint analysis of an integrated circuit (IC) may include defining a sequence of sample points for timing constraint analysis of an n&#xd7;n matrix, each sample point corresponding to a timing arc of the IC that includes data and reference slews; initially simulating extreme sample points of the matrix, according to the sequence, by substituting timing constraints from liberty files of the IC type for time values of the data slews and conducting a binary search for optimized timing constraints; and interpolating other sample points, according to the sequence, each of the other sample points having a starting bisection point that results from linear interpolation of the timing constraint analysis from adjoining sample points, which were simulated.

Methods and systems to reduce a number of simulations in a timing analysis

Disclosed is an integrated circuit design method that determines maximum direct currents for metal components and uses them as design constraints in the design flow in order to avoid/minimize electromigration failures. Short and long metal components are treated differently for purposes of establishing the design constraints. For a short metal component, the maximum direct current as a function of a given temperature for a given expected lifetime of the integrated circuit is determined, another maximum direct current is determined based on the Blech length, and the higher of these two is selected and used as the design constraint for that short metal component. For a long metal component, only the maximum direct current as a function of the given temperature for the given expected lifetime is determined and used as the design constraint. Also disclosed herein are associated system and program storage device embodiments for designing an integrated circuit.

Integrated circuit design method and system

A statistical single library that includes on-chip variation (OCV) is created for timing and power analysis of a digital chip design. Initially, library values for all cells of a digital chip design, including ranges for environmental and process parameters, are subject to a statistical model to create statistical timing for the ranges of the parameters. A statistical timing tool is applied across the ranges of the parameters to determine statistical corners for delay and input power to a subset of cells. The statistically determined delay and input power to the subset of cells is entered into the statistical single library. Each delay of each statistical corner for the subset of cells is compared with a chip sign-off statistical delay requirement of a test macro.

Statistical single library including on chip variation for rapid timing and power analysis

A method, apparatus and program product are provided for simulating a circuit. A plurality of elements of the circuit is represented by device models including pass/fail criteria. A circuit simulation program is executed on a hardware implemented processor where the circuit simulation program is configured to obtain simulation results from the device models in response to applied parameters. The circuit simulation program identifies a failure of one or more of the plurality of elements of the circuit based on the pass/fail criteria of the device models. The circuit simulation program is further configured to output the failures during simulation of the one or more of the plurality of elements that are identified in response to the applied parameters.

Model based simulation of electronic discharge and optimization methodology for design checking

A method of estimating decaps required for an IC during an initial floorplanning design phase begins by obtaining voltage variation waveforms for a plurality of nodes in a power distribution network of the IC. Next, the method computes a minimum value for each of the voltage variation waveforms and selects voltage variation waveforms below a minimum threshold value. Following this, an FDA is performed on the voltage variation waveforms below the minimum threshold value to create a set of frequency values. This involves performing an FFT on each of the voltage variation waveforms to obtain frequency domain data, wherein frequencies that cause a drop in voltage in the plurality of nodes are filtered. The method then sorts the frequency domain data, wherein the frequency domain data is arranged in order based on amplitude value, total power, frequency components, and/or amplitude of imaginary components.

Method and apparatus to target pre-determined spatially varying voltage variation across the area of the VLSI power distribution system using frequency domain analysis

A method for performing input/output (I/O) floor planning on an integrated circuit design is disclosed. User design data related to I/O circuit associated with each package pin is initially collected. The collected user design data is then sorted according to operating conditions. Next, an I/O behavioral model and a package model are chosen based on the sorted data. A simulation deck is dynamically built with appropriate operating conditions. Finally, a simulation is performed through a circuit simulator using the chosen I/O behavioral model and the operating conditions.

Method and apparatus for performing input/output floor planning on an integrated circuit design

Growing community of inventors

Essex Junction, VT, United States of America

Amol Anil Joshi