Cirrus Logic Inc.

Freescale Semiconductor,inc.

Sigmatel, Inc.

Ammisetti Prasad

John L Melanson

John Christopher Tucker

Murari L Kejariwal

Daniel John Allen

Karl Ernesto Thompson

Sherry Xiaohong Wu

Axel Thomsen

Chung-Kai Chow

Hua Yang

James Robert Feddeler

Shyam S Somayajula

Muari Kewariwal

An energy-efficient consumer device audio power output stage with gain control provides improved battery life and reduced power dissipation without clipping the audio output signal. A control circuit controls a power supply that supplies the power supply rails to the power amplified output stage. The voltage of the power supply rails is controlled in conformity with an input audio signal level, which may be determined from a volume control setting of the device and/or from a signal level detector that determines the amplitude of the signal being amplified. The gain applied to the audio input signal is reduced for a predetermined time period when a higher output voltage of the power supply is selected, to avoid clipping the audio output signal.

Energy-efficient consumer device audio power output stage with gain control

An energy-efficient consumer device audio power output stage with gain control provides improved battery life and reduced power dissipation without clipping the audio output signal. A power supply having a selectable operating mode supplies the power supply rails to the power amplified output stage. The operating mode is controlled in conformity with an input audio signal level, which may be determined from a volume control setting of the device and/or from a signal level detector that determines the amplitude of the signal being amplified. The gain applied to the audio input signal is reduced for a predetermined time period when a higher output voltage of the power supply is selected, to avoid clipping the audio output signal.

Energy-efficient consumer device audio power output stage

A signal processing system and method utilizes a multi-stage amplifier to amplify an input signal. The multi-stage amplifier uses a mixed set of voltage rails to improve the operating efficiency of at least one of the amplification stages while allowing other amplification stages to operate in a predetermined operating mode. Efficiency of at least one of the stages is improved by supplying at least one variable voltage rail to an amplification stage of the multi-stage amplifier. The variable voltage rail varies in response to changes in an input signal voltage to the amplification stage. Accordingly, at least one amplification stage utilizes a variable voltage rail, and all amplification stages are supplied with a set of voltage rails that provides sufficient input signal headroom, thus, providing amplification stage efficiency and adequate voltage to allow operation of all amplification stages.

Multi-stage amplifier with multiple sets of fixed and variable voltage rails

A programmable-gain amplifier has a first input node coupled to receive a first input signal and a control input coupled to receive a gain select signal. The programmable-gain amplifier includes a differential amplifier having a first input and a first output and a plurality of capacitors. A first terminal of each of the plurality of capacitors is coupled to the first input of the differential amplifier, and a second terminal of each of the plurality of capacitors is coupled to the first input node during a sampling phase of the programmable-gain amplifier and selectively coupled to the first output of the differential amplifier, based on the gain select signal, during a gain phase of the programmable-gain amplifier.

Switched-capacitor programmable-gain amplifier

An energy-efficient consumer device audio power output stage provides improved battery life and reduced power dissipation. A power supply having a selectable operating mode supplies the power supply rails to the power amplified output stage. The operating mode is controlled in conformity with the audio signal level, which may be determined from a volume control setting of the device and/or from a signal level detector that determines the amplitude of the signal being amplified. The power supply may be a charge pump in which the operating mode uses a capacitive divider to provide for selection of a power supply output voltage that is a rational fraction of the power supply output voltage in a full-voltage operating mode.

A switched capacitor circuit utilizes a pair of serially connected differential amplifiers that have plus inputs, minus inputs, plus outputs, and minus outputs. Feedback to the plus/minus inputs is in a first configuration relative to the output of the pair of differential amplifiers in a sampling mode and a second configuration in a hold mode. Similarly, the plus/minus inputs relative to the plus/minus outputs of the serially connected differential amplifiers is reversed between the sampling and hold modes.

Gain enhanced switched capacitor circuit and method of operation

A resistive circuit includes a first terminal and a second terminal and polycrystalline first and second resistive segments coupled between the first and second terminals. A third terminal A is coupled to the first resistive segment, and a third terminal B is coupled to the second resistive segment. The third terminal A has a first voltage with respect to the first terminal, and the third terminal B has a second voltage with respect to the second terminal. With this arrangement, the non-linearity of resistance of the first resistive segment at least partially compensates for non-linearity of resistance of the second resistive segment.

Compensation of field effect on polycrystalline resistors

An integrated circuit including at least one internal operational block, which includes test control circuitry for initiating a test mode and testing circuitry for verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. Pin control circuitry selectively outputs a test signal from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.

Non-invasive, low pin count test circuits and methods utilizing emulated stress conditions

A method of testing an internal block of an integrated circuit includes initiating a test mode and verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. A test signal is selectively output from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.

A chopping amplifier and method for chopping an input signal are disclosed. The chopping amplifier and method utilize at least two chopping amplifier stages. A chopping operation of an input signal is segmented across two or more chopping amplifier stages, and the two or more chopping amplifier stages are responsive to a master controller. Chop clock signals of the chopping amplifier stages are staggered so that they have non-overlapping periods and at least one of the chopping amplifier stages is not operating in an open loop at any given time. The non-overlapping periods are periodic so that a master chop clock of the master controller can be operated at a lower chop clock frequency. For every doubling of N number of chopping amplifier stages, magnitudes of chopping artifacts and aliased components are each respectively reduced by 3 dB.

Segmented chopping amplifier

A feed-forward operational amplifier including a dedicated summer circuit for summing a signal generated by a first amplifier stage of a feed-forward amplifier and a signal received from an external source to generate a sum signal and a second amplifier stage coupled to the summer circuit and receiving the sum signal. The second amplifier stage realizes a pole-zero doublet to decrease a unity gain frequency of the feed-forward operational amplifier.

Feed-forward operational amplifiers and methods of using the same

A sample and hold circuit including a sampling capacitor for storing a sample of an input signal, an output stage for outputting the sample stored on the sampling capacitor; and input circuitry for sampling the input signal and storing the sample on the sampling capacitor. The input circuitry includes an autozeroing input buffer which selectively samples the input signal during a first operating phase and holds a sample of the input signal during a second operating phase. The autozeroing input buffer cancels any offset error. The input circuitry also includes switching circuitry for selectively coupling the sampling capacitor with an input of the sample and hold circuitry during the second operating phase and to an output of the autozeroing input buffer during the first operating phase.

Sample and hold circuits and methods with offset error correction and systems using the same

A method of testing an integrated circuit includes setting a guardbanded limit for a parameter associated with an embedded node, a deviation from the guardbanded limit under a set of test conditions correlated with a failure of the integrated circuit across a range of operating conditions. A test is performed under the test conditions to detect deviations of the parameter from the guardbanded limit to detect failures of the integrated circuit over the range of operating conditions.

Growing community of inventors

Austin, TX, United States of America

Ammisetti Prasad