International Business Machines Corporation

Intel Corporation

Globalfoundries Inc.

Advanced Micro Devices Corporation

Freescale Semiconductor,inc.

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Amlan Majumdar

Jeffrey W Sleight

Anirban Basu

Guy M Cohen

Suman Datta

Jack T Kavalieros

Robert S Chau

Justin K Brask

Brian S Doyle

Yanning Sun

Cheng-Wei Cheng

Marko Radosavljevic

Sarunya Bangsaruntip

Isaac Lauer

Kuen-Ting Shiu

Josephine B Chang

Mark L Doczy

Uday Shah

Steven John Koester

Matthew V Metz

Jin Cai

Renee Tong Mo

Devendra K Sadana

Pranita Kerber

Zhibin Ren

Wilfried Haensch

Yu Zhu

Edward William Kiewra

Bruce Bennett Doris

Effendi Leobandung

Michael A Guillorn

Jeng-Bang Yau

Been-Yih Jin

Kangguo Cheng

Leland Chang

Brian L Ji

Uzma B Rana

Tak H Ning

Paul Michael Solomon

Chung-Hsun Lin

Sanjay C Mehta

Ramachandran Muralidhar

Eduard Albert Cartier

Robert H Dennard

Pranita Kulkarni

Balasubramanian S Haran

Mantu K Hudait

Xinhui Wang

Leathen Shi

Stefan Schmitz

Lidija Sekaric

David R Greenberg

Dinkar Virendra Singh

Kingsuk Maitra

Bala S Haran

Kangguo Chen

Jeffrey W Sleights

Juntao Li

Ghavam G Shahidi

Nicolas J Loubet

Keith E Fogel

Judson Robert Holt

Katherine Lynn Saenger

Arvind Kumar

Thomas N Adam

James M Blackwell

Ashima B Chakravarti

Robert J Miller

Woo-Hyeong Lee

Szu-Lin Cheng

Gen Pei

Suk Hoon Ku

Ryan M Martin

Jeremy John Kempisty

Arthur Gasasira

Ryan Matthew Mitchell

Louis Zuoguang Liu

Stephen J Koester

Leathen She

The density of deuterium or hydrogen within phase change material (PCM) of a PCM memory cell reduces the active defects in the amorphous phase of the PCM by passivating dangling bonds, which results in the PCM becoming easier to nucleate during the SET process of the PCM memory cell. Resultingly, the addition of deuterium or hydrogen within the PCM relatively increases the SET programming voltage window of the PCM memory cell compared with a similar PCM cell without.

Phase change material including deuterium

A structure includes a semiconductor substrate, a buffer layer disposed over the semiconductor substrate, an oxide layer disposed over the buffer layer, and a fin including a semiconductor material disposed over the oxide layer.

Device isolation using preferential oxidation of the bulk substrate

A semiconductor device comprises a first layer of a substrate arranged on a second layer of the substrate the second layer of the substrate including a doped III-V semiconductor material barrier layer, a gate stack arranged on a channel region of the first layer of a substrate, a spacer arranged adjacent to the gate stack on the first layer of the substrate, an undoped epitaxially grown III-V semiconductor material region arranged on the second layer of the substrate, and an epitaxially grown source/drain region arranged on the undoped epitaxially grown III-V semiconductor material region, and a portion of the first layer of the substrate.

III-V transistor device with self-aligned doped bottom barrier

A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Method for fabricating transistor with thinned channel

A structure includes a semiconductor substrate, a semiconductor buffer layer disposed over the semiconductor substrate, an oxide layer disposed over the buffer layer, and a fin including a semiconductor material disposed over the oxide layer. The semiconductor material has an oxidation rate different from an oxidation rate of the buffer layer.

Techniques for forming dual III-V semiconductor channel materials to enable fabrication of different device types on the same chip/wafer are provided. In one aspect, a method of forming dual III-V semiconductor channel materials on a wafer includes the steps of: providing a wafer having a first III-V semiconductor layer on an oxide; forming a second III-V semiconductor layer on top of the first III-V semiconductor layer, wherein the second III-V semiconductor layer comprises a different material with an electron affinity that is less than an electron affinity of the first III-V semiconductor layer; converting the first III-V semiconductor layer in at least one second active area to an insulator using ion implantation; and removing the second III-V semiconductor layer from at least one first active area selective to the first III-V semiconductor layer.

Hybrid III-V technology to support multiple supply voltages and off state currents on same chip

A method includes providing a structure including a substrate, a buffer layer formed on the substrate and a semiconductor layer formed on the buffer layer, etching the semiconductor layer so as to form a fin and exposing the buffer layer, etching the buffer layer such that a portion of the buffer layer, disposed under the fin, is exposed, and oxidizing the buffer layer and fin so as to form an oxide layer under the fin.

A structure includes a semiconductor substrate, a semiconductor buffer layer disposed on the semiconductor substrate, an oxide layer disposed on the buffer layer, and a fin including a semiconductor material disposed on the oxide layer. The fin and the buffer layer are epitaxially aligned to the semiconductor substrate.

A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

Extreme high mobility CMOS logic

An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second III-V semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.

III-V field effect transistor on a dielectric layer

A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is highly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of second epitaxial layer to expose a portion of the first conformal epitaxial layer, selectively removing a portion of the first conformal epitaxial layer to expose a portion of the fin and thereby form a trench, and forming a gate within the trench.

Fabrication process for mitigating external resistance of a multigate device

A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.

Planar III-V field effect transistor (FET) on dielectric layer

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White Plains, NY, United States of America

Amlan Majumdar