Rochester Institute of Technology

Amlan Ganguly

Mark Allen Indovina

Sathwika Bavikadi

Purab Ranjan Sutradhar

Mark Connolly

Sai Manoj Pudukotai Dinakarrao

A processing element includes a PIM cluster configured to read data from and write data to an adjacent DRAM subarray, wherein the PIM cluster has a plurality of processing cores, each processing core of the plurality of processing cores containing a look-up table, and a router connected to each processing core, wherein the router is configured to communicate data among each processing core; and a controller unit configured to communicate with the router, wherein the controller unit contains an executable program of operational decomposition algorithms. The look-up tables can be programmable. A DRAM chip including a plurality of DRAM banks, each DRAM bank having a plurality of interleaved DRAM subarrays and a plurality of the PIM clusters configured to read data from and write data to an adjacent DRAM subarray is disclosed.

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W. Henrietta, NY, United States of America

Amlan Ganguly