Samsung Electronics Co., Ltd.

International Business Machines Corporation

Cadence Design Systems, Inc.

Adaptive Chips, Inc.

Amjad Z Qureshi

Kab Ju Moon

Le Trong Nguyen

Jae Cheol Son

David Brian Ruth

Kevin Chiang

Donovan Scott Popps

Randall Clay Itskin

William R Hardell, Jr

Sanghyeon Baeg

Hoyoung Kim

Cliff Reader

John Carmine Pescatore, Jr

Mark Frederiksen

Babu Chilukuri

Tim Lu

A system-on-chip (SOC) () is interfaced with a memory () formed by a plurality of stacked memory integrated circuit dies (-). The SOC () includes a memory controller () that has a built-in self-test (BIST) system () for performing the testing and repair of memory (). BIST system () includes a microcode processor () that communicates externally to the SOC () through a Joint Test Action Group interface () and is coupled to a BIST state machine () for executing a memory specific test sequence to detect faults in memory (). The microcode processor () further communicates with a repair state machine () to execute memory specific repair procedures responsive to memory faults being detected.

Apparatus and method for built-in test and repair of 3D-IC memory

A method, system and apparatus of a secure debug interface and memory of a media security circuit and method are disclosed. In one embodiment, a host processor, an external hardware circuit to encrypt an incoming data bit communicated to a debug interface using a debug master key stored at a pointer location of a memory (e.g., the memory may be any one of a flash memory and/or an Electrically Erasable Programmable Read-Only Memory (EEPROM)) and to decrypt an outgoing data bit from the debug interface using the debug master key, and a media security circuit having the debug interface to provide the pointer location of the memory having the debug master key to the external hardware circuit.

Secure debug interface and memory of a media security circuit and method

A computer system includes three processors capable to operate concurrently&mdash;a scalar processor, a vector processor, and a bitstream processor. In encoding or decoding of video data, the vector processor performs operations that can be efficiently performed by a single instruction multiple data processor, for example, a discrete cosine transform (DCT) and motion compensation. The bitstream processor performs Huffman and RLC encoding or decoding. The bitstream processor can switch contexts to enable the computer system to process several data streams concurrently. The scalar and vector processors can be programmed to execute a single arithmetic or Boolean instruction. The bitstream processor cannot be programmed to execute a single arithmetic or Boolean instruction, but can be programmed to perform an entire video data processing operation. The computer system can handle different video standards. Different Huffman encoding and decoding tables are coded to share memory. Logic is supplied to derive correct Huffman codes from the coded tables stored in the shared memory.

Methods and apparatus for processing video data

To reduce latency on a shared bus during bus arbitration, a novel shared bus system uses device select lines between a bus arbiter and the bus devices to select the bus slave concurrently with the granting of the shared bus to the bus master. Specifically, a bus device requests the use of the shared bus by driving an active state on a bus request terminal and driving a destination ID value corresponding to the desired bus slave to the bus arbiter. The bus arbiter then drives an active state on a bus grant output terminal coupled to the bus grant input terminal of the requesting device. Concurrently, the bus arbiter drives an active state on the device select output terminal coupled to the device select input terminal of the desired bus slave. In addition posted read request tagging can be simplified using a transaction ID bus to supplement the shared bus.

Shared bus system with transaction and destination ID

To reduce latency for priority requests in a bus system, non-priority requests to a bus device are separated from priority requests so that the priority requests can be processed before the non-priority requests. Priority requests are transferred over a priority request bus. Standard non-priority requests are sent over a shared bus coupled to several bus devices. One of the bus devices contains a request buffer to receive non-priority requests from the shared bus and a priority buffer to receive priority requests from the priority request bus. Requests in the priority buffer are processed before requests in the request buffer. In one embodiment, a multiplexer having input ports coupled to the request buffer and the priority buffer is configured so that the multiplexer outputs priority requests if there are priority requests in the priority buffer. Some embodiments of the bus communication system incorporate a priority bypass bus which transfers priority data directly to a peripheral device coupled to the first bus device.

Priority request and bypass bus

A DMA controller has a first data buffer and a second data buffer. First data from a first bus can be loaded into the first data buffer at the same time that second data from a second bus is loaded into the second data buffer. Once the data is present in the first and second data buffers, the first data in the first data buffer can be supplied to the second bus at the same time that the second data in the second data buffer is supplied to the first bus (or alternatively to a third bus). In some embodiments, the second bus is a high speed parallel bus and the first and third data buses are I/O data buses for coupling the DMA controller to codecs. In some embodiments, data from the first data bus can be loaded into the first data buffer at the same time that data in the second data buffer is supplied to the third data bus. An address generator generates addresses onto the second data bus for the transfer of data between the DMA controller and the second data bus.

Simultaneous data transfer through read and write buffers of a DMA

A FIFO storage circuit stores data transferred over a data bus in data groups having of one or more data units. The FIFO buffer includes a number of storage locations each configured to store a single unit of data. Each data groups on the data bus is accompanied by data-size information. A storage-location availability decoder receives the data-size information and allocates a number of consecutive storage locations in the FIFO storage circuit to allow for storage of the incoming data group. The FIFO then stores each unit of the data group, along with a data tag common to each unit, in consecutive storage locations. The next stored data group is then assigned a new data tag. The FIFO storage circuit reads from the storage locations in order of data tag. Checking consecutive storage locations for equivalent data tags enables the FIFO storage circuit to output the appropriate number of units for each data group. Further, assigning unique sequential data tags to each data group allows the FIFO storage circuit to read the contents of FIFO buffer 200 in the appropriate order.

Byte-writable two-dimensional FIFO buffer having storage locations with

A DMA controller receives size data in association with a DMA request. If first size data is received, a first amount of data (for example, one word) is transferred through the DMA controller for the DMA request. If, on the other hand, second size data is received, then a second amount of data (for example, two words) is transferred through the DMA controller for the DMA request. In the event that a DMA request cannot be serviced when received, the DMA request is stored in the DMA controller for later servicing. Size data for a DMA request is stored so that the size of the data transfer will be known when the stored DMA request is serviced. Using this size data, a single DMA channel can support data transfers of different sizes. In some embodiments, size data is used to increment a DMA current address register by the correct amount after the data associated with the size data is transferred through the DMA controller.

DMA controller which receives size data for each DMA channel

A DMA controller receives a DMA request from a DMA channel and generates a transaction request ID identifying the requested transaction as well as a codec ID identifying the DMA channel. The codec ID is stored in the DMA controller in association with the transaction request ID. The DMA controller obtains control of the bus and outputs a transaction request onto the bus along with the transaction request ID. The DMA controller then relinquishes control of the bus. A device on the bus returns the transaction request ID when it responds (the transaction request ID is 'tagged' to the response). The DMA controller uses the returned transaction request ID to look up the codec ID stored in the DMA controller in association with that transaction request ID. The DMA controller uses the codec ID to associate the response with the correct DMA channel. In the event the split transaction is a posted read, the DMA controller uses the returned transaction request ID to supply the data to the DMA channel that issued the DMA request.

DMA controller with channel tagging

A multi-standard start code detector system receives an incoming compressed video bit stream. The compressed video bit stream includes start codes interspersed between variable length bit streams. Assuming error-free useful data, zero stuffing bits preceding a next start code are rapidly discarded on a bit group-wise basis. A group of current bits are processed by comparing them to a start code feature pattern. If a match is not detected, the entire group of bits is concurrently replaced by a next group. However, because the zero stuffing bits are of variable length, the exact position of the start code pattern is unknown. Preceding each replacement operation, the next group of bits is processed to predetect a start code feature. Upon predetecting a start code feature, the replacement operation is modified to ensure that a group of current data bits will include the start code feature pattern. This allows the number of searched for patterns to be reduced and streamlines the comparison operation. Additionally, the multi-standard start code detector system implements an error handling operation that effectively searches and discards bits on a group-wise basis. The error handling operation compares a group of current data to a pattern known to subsequently occur and that is not included in useful data. In one embodiment, the error handling operation compares the bit group to a zero stuffing bit pattern. Upon detection of the zero stuffing bits, the error handling operation proceeds in accordance with the start code feature detection operation.

Bit stream signal feature detection in a signal processing system

An SDRAM initialization and power on system includes a configuration validation circuit for registers in a Memory Controller Unit and a Power On Sequence State Machine. The validation circuit asserts a status signal Config.sub.-- OK if the configuration of the memory control unit is correct. The signal Config.sub.-- OK enables the Power On Sequence State Machine. A status signal PowerOn.sub.-- OK is asserted once the SDRAMs have been initialized. The SDRAMs are not accessible for normal operation unless Config.sub.-- OK and PowerOn.sub.-- OK are asserted. By monitoring the two signals Config.sub.-- OK and PowerOn.sub.-- OK, debugging can be much more efficient and corruption of SDRAMs with bad data can be avoided.

Structure and method for memory initialization and power on

A PCI interface includes a PCI core that operates at the PCI bus frequency and glue logic which provides an interface to a higher frequency clock domain. The glue logic includes FIFO buffers for addresses and data coming from or going to the PCI bus, and synchronizers for control signals coming from or going to the PCI core. In one embodiment, a novel synchronizer includes three flip-flops at least two of which are JK flip-flops.

PCI interface synchronization

A method and system for simultaneous retrieval of snoop address information in conjunction with the retrieval/storing of a cache line load/store operation. The method and system are implemented in a data processing system comprising at least one processor having an integrated controller, a cache external to the at least one processor, and an interface between the at least one processor and the external cache. The external cache includes a tag array and a data array. Standard synchronous static Random Access Memory (RAM) is used for the tag array, while synchronous burst made static RAM is used for the data array. The interface includes a shared address bus, a load address connection and an increment address connection. A cache line load/store operation is executed by placing an address for the operation on the shared address bus, and latching the address with the external cache using a signal from the load address connection. Thereafter, the latched address is incremented in response to a signal from the increment address connection. This allows the shared address bus to be used for execution of snoop operations simultaneously with the retrieval/storage of a cache line load/store operation.

Method and system for simultaneous processing of snoop and cache

JTAG test logic and a memory controller place an SDRAM in a self refresh mode prior to beginning JTAG testing. The memory controller can complete a current memory access and otherwise prepare for the JTAG test. During the JTAG test, self refresh mode operation of the SDRAM retains data without the need for a clock signal or refresh signals which are suspended for the JTAG test. Accordingly, after the JTAG test, circuit operation can continue without reinitializing data in the SDRAM.

Structure and method for SDRAM dynamic self refresh entry and exit using

A system and method for converting data with one error correction code format to data with a different error correction code format, including provisions for correcting the errors in the input data and checkbits. The invention reduces the levels of logic needed to accomplish the conversion. In one form, checkbits for the converted data are generated from the input data at the same time that the input data correction syndromes are generated from the input data and checkbits. Multiple sets of error pointers are then used to simultaneously correct both the converted data and the converted data checkbits.

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San Jose, CA, United States of America

Amjad Z Qureshi