Intel Corporation

Amjad M Khan

Bruce Querbach

David G Ellis

Eric S Gayles

Eshwar Gollapudi

Inder M Sodhi

Ryan Donovan Wells

Zeev Offen

Jay Joseph Nejedlo

Sean R Babcock

Michael J Tripp

Ali Muhtaroglu

Mike J Tripp

Marco A Vindas Vargas

Luis Briceno Guerrero

I/O logic can be separated into critical and non-critical portions, with the non-critical portions being powered down during processor idle. The I/O logic is separated into gate logic and ungated logic, where the ungated logic continues to be powered during a processor deep sleep state, and the gated logic is powered off during the deep sleep state. A power control unit can trigger the shutting down of the I/O logic.

Split deep power down of I/O module

Embodiments of the invention provide a logic simulation having a controllable delay model implemented therein that may be used to validate AC I/O loopback design in a pre-silicon environment by introducing delay models that allow the logic simulators to simulate analog behavior. For one embodiment of the invention, a fixed processor ratio is selected and delay statements of the hardware description language correspond to a specific time delay. These fixed values provide the ability to accurately determine and adjust delay in an analog simulation.

Methods and apparatuses for validating AC I/O loopback tests using delay modeling in RTL simulation

A multi-bit test value is loaded into a built-in latch of the IC component, and a pad of the component is selected for testing. A number of different sequences of test values are automatically generated, based on the stored test value, without scanning-in additional multi-bit values into the latch. A signal that is based on the different sequences of test values is driven into the selected pad and looped back. A difference between the test values and the looped back version of the test values is determined, while automatically adjusting driver and/or receiver characteristics to determine a margin of operation of on-chip I/O buffering for the selected pad.

Automatic self test of an integrated circuit component via AC I/O loopback

A built-in self test (BIST) unit, of a primary integrated circuit (IC) component of a computer system, is programmed or hardwired with a test pattern. The test pattern is launched in multiple test cycles, to test an interconnect bus of the computer system or perform a device validation test of the component. A pin assignment of the pattern is automatically changed after each test cycle, without requiring re-programming of the BIST unit to do so.

Push button mode automatic pattern switching for interconnect built-in self test

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Folsom, CA, United States of America

Amjad M Khan