Micron Technology Incorporated

Amitava Majumdar

Nevil N Gajera

Shawn D Lyonsmith

Danilo Caraccio

Lingming Yang

Radhakrishna Kotti

Rajesh Kamana

Sandeep Krishna Thirumala

Sujeet V Ayyapureddi

Karthik Sarpatwari

Zengtao T Liu

Hongmei Wang

Yang Lu

Edmund Gieske

Ervin T Hill

Anandhavel Nagendrakumar

Ankush Lal

Marlon W Hug

Gordon A Haller

Ameen D Akel

Frank F Ross

Cagdas Dirik

Ted Lyle Taylor

Ahmed Nayaz Noemaun

Kirthi Shenoy

Qianlan Liu

Greg S Hendrix

Steve K McCandless

Pradeep Ramachandran

Adam D Gailey

Krunal Patel

Robert Michael Walker

Rajasekhar Venigalla

Elliott Clifford Cooper-Balis

Pavan Reddy K Aella

Patrick Daniel White

Mallesh Rajashekharaiah

Daniele Balluchi

Markus H Geiger

Jessica Chen

Mohammed Ebrahim Hargan

Francesco Douglas Verna-Ketel

Xuan-Anh Tran

Elliott C Cooper-balis

Xuan Anh Tran

Scott Garner

Chia Wei Chang

Niccolo′ Izzo

A method of predicting virtual metrology data for a wafer lot that includes receiving first image data from an imager system, the first image data relating to at least one first wafer lot, receiving measured metrology data from metrology equipment relating to the at least one first wafer lot, applying one or more machine learning techniques to the first image data and the measured metrology data to generate at least one predictive model for predicting at least one of virtual metrology data or virtual cell metrics data of wafer lots, and utilizing the at least one generated predictive model to generate at least one of first virtual metrology data or first virtual cell metrics data for the first wafer lot.

System for predicting properties of structures, imager system, and related methods

In a memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, the data is corrected and written back to the same memory location. The memory location is re-read. If bit errors are again identified, the memory location is marked for soft or hard repair. If, upon rereading the memory location, additional bit errors are identified, a historical record of memory errors is reviewed to determine if bit errors have occurred previously at the same memory location. If yes, the memory location is again marked for a soft post package repair or a hard post package repair.

Error detection, correction, and media management on a dram device

Error detection, correction, and media management on a memory device

In a compute express link (CXL) memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, steps are taken to determine if the memory location requires no repair, soft repair, or hard repair. The data is corrected and written back to a new memory location which is memory-mapped to the original location, thus effecting the soft- or hard-repair. The present system and method does not repair the entire row of memory, but only repairs the specific die(s) that exhibit memory error in the row.

Selective per die DRAM PPR for memory device

Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.

Finite time counting period counting of infinite data streams

Systems and methods for area-efficient mitigation of errors that are caused by row hammer attacks and the like in a memory media device are described. The counters for counting row accesses are maintained in a content addressable memory (CAM) the provides fast access times. The detection of errors is deterministically performed while maintaining a number of row access counters that is smaller than the total number of rows protected in the memory media device. The circuitry for the detection and mitigation may be in the memory media device or in a memory controller to which the memory media device attaches. The memory media device may be dynamic random access memory (DRAM).

Area-optimized row hammer mitigation

An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.

Row hammer telemetry

Practical, energy-efficient, and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The mitigation may be implemented on a per-bank basis. The memory media device may be DRAM.

Practical and efficient row hammer error detection

Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

Memory device security and row hammer mitigation

Systems, apparatuses, and methods can include a multi-stage cache for providing high reliability, availability, and serviceability (RAS). The multi-stage cache memory comprises a shadow DRAM, which is provided on a volatile main memory module, coupled to a memory controller cache, which is provided on a memory controller. During a first write operation, the memory controller writes data with a strong error correcting code (ECC) from the memory controller cache to the shadow DRAM without writing a RAID (Redundant Arrays of Inexpensive Disks) parity data. During a second write operation, the memory controller writes the data with the strong ECC and writes the RAID parity data from the shadow DRAM to a memory device provided on the volatile main memory module.

Shadow DRAM with CRC+RAID architecture, system and method for high RAS feature in a CXL drive

Provided is a memory system comprising a plurality of memory channels each having a parity bit, a redundant array of independent devices (RAID) parity channel, and a controller of the memory system. The controller is configured to receive a block of data for storage in the memory channels and determine at least one of (i) when a data traffic demand on the memory channels is high and (ii) when a data traffic demand on the memory channels is low. Upon determining the data traffic demand is low, writing the block of data for storage in the memory channels and concurrently updating the parity bits and the RAID parity channel for the stored block of data. Upon determining the data traffic demand is high, only writing the data for storage in the memory channels.

Instant write scheme with delayed parity/raid

Provided is a memory system including a plurality of memory submodules and a controller. Each submodule comprises a plurality of memory channels, each channel having a parity bit and a redundant array of independent devices (RAID) parity channel. The controller is configured to receive a block of data for storage in the plurality of memory submodules and determine whether a level of data traffic demand for a first of the plurality of submodules is high or low. When the data traffic demand is low, (i) writing a portion of the block of data in the first of the plurality of submodules and (ii) concurrently updating the parity bit and the RAID parity channel associated with the block of data. When the data traffic demand is high, (i) only writing the portion of the block of data in the first of the plurality of submodules and (ii) deferring updating of the parity bits and the RAID parity channel associated with the block of data.

Method and memory system for writing data to dram submodules based on the data traffic demand

Methods, systems, and devices for electron beam probing techniques and related structures are described to enable inline testing of memory device structures. Conductive loops may be formed, some of which may be grounded and others of which may be electrically floating in accordance with a predetermined pattern. The loops may be scanned with an electron beam and image analysis techniques may be used to generate an optical pattern. The generated optical pattern may be compared to an expected optical pattern, which may be based on the predetermined pattern of grounded and floating loops. An electrical defect may be determined based on any difference between the generated optical pattern and the expected optical pattern. For example, if a second loop appears as having a brightness corresponding to a grounded loop, this may indicate that an unintended short exists. Fabrication techniques may be adjusted for subsequent devices to correct identified defects.

Electron beam probing techniques and related structures

Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.

Socket design for a memory device

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Boise, ID, United States of America

Amitava Majumdar