Vmware, Inc.

Cypress Semiconductor Corporation

Amitabha Banerjee

Lenin Singaravelu

Rishi Mehta

Xiaochuan Shen

Somnath Paul

Ayyappan Veeraiyan

Seongbeom Kim

Ruijin Zhou

Jay Kishora Gupta

Debessay Fesehaye Kassa

Xiaobo Huang

In order to facilitate efficient and scalable lookup of current hop limits of transmitted packets, a communications device embeds hop limit values along with other connection parameters in a connection data structure. To transmit a packet for a particular connection, the communications device retrieves the data structure for the particular connection and applies the hop limit value embedded in the data structure to the packet for transmission. To keep track of the hop limits being embedded in different data structures of different connections, the communications device use a binary search in which each node of the search tree correspond to a different connection. The communications device maintains one such search tree per communications interface.

Fast lookup and update of current hop limit

Certain embodiments described herein are generally directed to improving performance of one or more machines within a system by clustering multidimensional datasets relating to the performance of the machines using inter-group dissimilarities between groups of the dataset. The method for improving performance of one or more machines within a system, includes forming a multidimensional dataset having a plurality of groups using performance related data associated with one or more machines in the system, clustering the plurality of groups into one or more clusters based on intergroup dissimilarities between the plurality of groups, identifying one or more anomalous clusters from among the one or more clusters, identifying the one or more anomalous groups in the one or more anomalous clusters, and adjusting a configuration of the system to improve the performance of the one or more machines corresponding to the one or more anomalous groups.

Group clustering using inter-group dissimilarities

Systems and methods described herein align various types of hypervisor threads with a non-uniform memory access (NUMA) client of a virtual machine (VM) that is driving I/O transactions from an application so that no remote memory access is required and the I/O transactions can be completed with local accesses to CPUs, caches, and the I/O devices of a same NUMA node of a hardware NUMA system. First, hypervisor of the VM detects whether the VM runs on a single or multiple NUMA nodes. If the VM runs on multiple NUMA nodes, a NUMA client on which the application is executing the I/O transactions is identified and knowledge of resource sharing between the NUMA client and its related hypervisor threads is established. Such knowledge is then utilized to schedule the NUMA client and its related hypervisor threads to the same NUMA node of the NUMA system.

Systems and methods for non-uniform memory access aligned I/O for virtual machines

Systems and methods for preferentially assigning virtual machines (VMs) on a particular NUMA node with network queues on the same NUMA node are described. A load balancer process on a host assigns multiple VMs to network queues. The assignment of the VMs to a network queues is performed with a bias toward assigning VMs using a particular NUMA node to network queues on the same NUMA node. A scheduler on the host assigns VMs to NUMA nodes. The scheduler is biased toward assigning VMs to the same NUMA node as the PNIC and/or the same NUMA node as a network queue assigned to the VM.

NUMA I/O aware network queue assignments

A method and apparatus for assembling non-aligned packet fragments over multiple cycles is described. In one embodiment, the invention is a method. The method includes rotating a non-aligned data fragment within a rotate register based on a tail pointer of a prior data fragment to form a rotated data fragment. The method also includes outputting the rotated data fragment to a double width bus as a double width image of the rotated data fragment. The method further includes selectively copying the double width image of the rotated data fragment from the bus to a location logically following the prior data fragment in a destination register.

Method and apparatus for assembling non-aligned packet fragments over multiple cycles

A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic. A memory has an address bus coupled to the channel control logic and the pointer and flag logic.

Growing community of inventors

San Jose, CA, United States of America

Amitabha Banerjee