Texas Instruments Corporation

Amitabh Menon

Timothy David Anderson

Joseph R Zbiciak

Kai Chirca

Ajit Deepak Gupte

David J Hoyle

Gary L Swoboda

Matthew D Pierson

Joseph Raymond Michael Zbiciak

Venkatesh Natarajan

David R Matt

Subash Chandar Govindarajan

Madathil R Karthikeyan

Vijay Sindagi

A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the master, usually a CPU originating the request based on a Privilege Identifier that accompanies each memory access request. Deputy masters such as DMA controllers inherit the Privilege Identifier of the originating master. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the master originating the request.

Memory management unit that applies rules based on privilege identifier

A prefetch cancelation arbiter improves access to a shared memory resource by arbitrarily canceling speculative prefetches. The prefetch cancelation arbiter applies a set of arbitrary policies to speculative prefetches to select one or more of the received speculative prefetches to cancel. The selected speculative prefetches are canceled and a cancelation notification of each canceled speculative prefetch is sent to a higher-level memory component such as a prefetch unit or a local memory arbiter that is local to the processor associated with the canceled speculative prefetch. The set of arbitrary policies is used to reduce memory accesses to the shared memory resource.

Prefetcher with arbitrary downstream prefetch cancelation

A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the requestor, based on a Privilege Identifier that accompanies each memory access request. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the requestor originating the request. A set of mapping registers allow flexible mapping of each Privilege Identifier to the appropriate access permission. The segment registers translate the logical address from the requestor to a physical address within a larger address space.

Flexible memory protection and translation unit

A memory validation manager reserves a block of time for exclusive accesses to a memory bank having lines of memory for which validation codes provide a degree of error detection and correction for each memory line. The memory validation manager reads, processes, and corrects at least some of the contents of each memory line based on indications of validity encountered for each memory line. New data is written in response to a validation code. Likewise, a valid field for each line can be updated and a new validation code written for a memory when the valid field indicates that a validation code has not yet been written for a memory line. The memory validation manager processes data read from a first memory line while either reading or writing to another memory line to minimize the latency of the process of scrubbing memory lines.

Memory controller with automatic error detection and correction

An arbiter is provided for arbitrating for access to a shared resource by a plurality of requesters and by a background requester in a processing system. A priority value is assigned to each of the plurality of requestors. A multilayer arbitration contest is performed to resolve each conflict in transaction requests to the shared resource, however, a requester of the plurality of requesters having a highest priority value does not always win an arbitration contest. An arbitration contest will be overridden whenever the background requester initiates a transaction request, such that the background requester always wins the overridden arbitration contest. The shared resource is accessed by the winner of each arbitration contest.

Multilayer arbitration for access to multiple destinations

A memory management and protection system that incorporates device security features that support a distributed, shared memory system. The concept of secure regions of memory and secure code execution is supported, and a mechanism is provided to extend a chain of trust from a known, fixed secure boot ROM to the actual secure code execution. Furthermore, the system keeps a secure address threshold that is only programmable by a secure supervisor, and will only allow secure access requests that are above this threshold.

Device security features supporting a distributed shared memory system

This invention makes each register bypass forwarding register explicitly addressable in software. Software chooses whether to access the forwarding register immediately eliminating the need for complex automatic detection. Each instruction executes and always writes its result into the forwarding register. Writing this data into the register file in the next cycle is optional as selected by the destination register file number. This invention separates registers storing predication data from the register file. This separation removes the speed problem by enabling scheduling of the predication computation out of the critical path.

Register file bypass with optional results storage and separate predication register file in a VLIW processor

A VLIW processor has a hierarchy of functional unit clusters that communicate through explicit control in the instruction stream and store data in register files at each level of the hierarchy. Explicit instructions transfer values between sub-clusters through a cluster level switch network. Transfer instructions issue in dedicated instruction issue slots in parallel with instructions that perform computation in functional units. The switch network can perform permutations on the data being moved. The switch network enables for operands to be broadcast between the sub-clusters, global register file and memory.

Inter-cluster communication network and heirarchical register files for clustered VLIW processors

A programmable address decoder is common to the on-chip ROM and on-chip RAM. The programmable address decoder conditionally routes accesses to portions of the ROM to the RAM. The ROM address space is mapped to RAM via a set of configuration registers. This permits patched ROM program code and data table to be stored in on-chip RAM. The patched code and configuration data is stored in an off-chip non-volatile memory. This patch code and the configuration to use is loaded into the RAM and configuration registers on system bootstrap procedure.

Multiple patches to on-chip ROM in a processor with a multilevel memory system without affecting performance

A log shifter shifting an operand left or right while minimizing the number of multiplexor stages. The log shifter may contain a set of multiplexor stages, with at least one multiplexor stage shifting a data value to the right and at least one other multiplexor stage shifting to the right. Left and right shifts may thus be obtained by using a single set of multiplexor stages. As a result, time delays and area consumed may be reduced when the upper/lower end of a desired shift value range does not equal 2&#x2212;1, wherein Q equals an integer.

Shifting an operand left or right while minimizing the number of multiplexor stages

Multiple register input multiplexors select a respective one of the results generated by operation units, and store the selected results in respective architecture registers as specified by the corresponding instructions (from which the results are generated). A forwarding multiplexor receives the results before the results are provided to the register input multiplexors, and selects one of the results for use as an operand for execution of a dependent instruction. As the forwarding multiplexor receives the results at a point before the inputs of the register input multiplexors, the time duration required to forward the results may be minimized, and a greater instruction throughput performance may be attained in a processor.

Forwarding the results of operations to dependent instructions more quickly via multiplexers working in parallel

A reconfigurable datapath ( ), which may be alternatively configured for various debug modes. These modes include a breakpoint mode ( ), counter mode ( ), DMA mode ( ), and PSA mode ( ). Each configuration uses one or more of two bitcell units: a register bitcell unit ( ) and a comparator bitcell unit ( ). The inputs and interconnections of these bitcell units ( ) determine the configuration, and hence the mode, for which they are to be used.

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Lewisville, TX, United States of America

Amitabh Menon