Advanced Micro Devices Corporation

Ati Technologies Ulc

Hewlett-packard Company

Amitabh Mehra

Anil Harwani

William R Alverson

Grant E Ley

Joshua Taylor Knight

Jerry A Ahrens

Jerry Anton Ahrens, Jr

Richard Martin Born

Jayesh Joshi

Yasuko Eckert

Vilas K Sridharan

Sudhanva Gurumurthi

Steven Kommrusch

Scott E Swanstrom

Xiaojie He

Michael L Golden

Sriram Srinivasan

Alicia Wen Ju Yurie Leong

Mustansir M Pratapgarhwala

Gokul Subramani Ramalingam Lakshmi Devi

Sankaranarayanan Gurumurthy

Divya Madapusi Srinivas Prasad

Vikram Ramachandra

Jeffrey Richard Rearick

Shidhartha Das

Alex W Schaefer

William Robert Alverson

Grant Evan Ley

Sneha Komatireddy

Xiuting Kaleen C Man

Dana Glenn Lewis

David M Dahle

Krishna Sai Bernucho

Dirk J Robinson

Bobby D Young

Kenneth Mitchell

Charles Sy Lee

John William Abshier

Charles Sum Yuen Lee

Jeffrey N Burley

Bobby Young

System memory training with chipset attached memory is described. In accordance with the described techniques, a request is received to train a system memory of a device. Responsive to the request, contents of the system memory are transferred to a chipset attached memory. The device is operated using the contents from the chipset attached memory. While the device is being operated using the contents from the chipset attached memory, the system memory is dynamically trained. After the training is complete, the contents are transferred back from the chipset attached memory to the trained system memory.

System memory training with chipset attached memory

Duplicating memory content with chipset attached memory is described. In accordance with the described techniques, contents of a system memory are duplicated on a chipset attached memory over a chipset link. Memory requests are serviced using the contents of the system memory and the contents on the chipset attached memory. Servicing the memory requests includes servicing a first portion of a read request using the contents of the system memory and a second, remaining portion of the read request using the contents on the chipset attached memory. Servicing the memory requests further includes communicating a write request to the system memory and to the chipset attached memory.

Duplicating memory content with chipset attached memory

Package lids with carveouts configured to expose lights directly connected to an internal component of a processor are described. Lid carveouts are configured to precisely align and mechanically secure a cooling device to the package lid by receiving protrusions of the cooling device via a press fit connection, while maintaining visibility of lights directly connected to processor internal components when the cooling device is connected. Lid carveouts are further configured to expose one or more connectors disposed on a processor surface that supports its internal component. When contacted by corresponding connectors of an auxiliary device, such as a light not integrated into a processor package or a cooling device, the lid carveouts enable direct connections between the package's internal components and the auxiliary device.

Lid carveouts for processor lighting

Extended training for memory is described. In accordance with the described techniques, a training request to train a memory with extended training is received. The extended training corresponds to a longer amount of time than a default training. The extended training of the memory is performed using a set of target memory settings. In one or more implementations, the extended training is performed during a boot up phase of the computing device.

Extended training for memory

Automated memory overclocking is described. In accordance with the described techniques, one or more sets of overclocked memory settings of a memory are automatically selected for performance testing and stability testing of the memory. The one or more sets of the overclocked memory settings are tested for performance of the memory and a performance indication is output for each of the one or more sets of the overclocked memory settings. The one or more sets of the overclocked memory settings are tested for stability of the memory and a stability indication is output for each of the one or more sets of the overclocked memory settings. One of the one or more sets of the overclocked memory settings are selected as optimized overclocked memory settings for the memory.

Automated memory overclocking

An exemplary computing device includes a plurality of circuits and/or a plurality of in-situ monitors configured to generate outputs that indicate one or more operating conditions of the circuits. The computing device also includes a system management unit configured to detect a potentially faulty voltage-to-frequency ratio implemented by one of the circuits based at least in part on one or more of the outputs. The system management unit is also configured to modify the potentially faulty voltage-to-frequency ratio based at least in part on one or more of the outputs. Various other devices, systems, and methods are also disclosed.

Devices, systems, and methods for detecting and mitigating silent data corruptions via adaptive voltage-frequency scaling

Physical adjustment to system memory with chipset attached memory is described. In accordance with the described techniques, an indication for making one or more physical adjustments to system memory of a device is received. Contents of the system memory are transferred via a chipset link to a chipset attached memory. The device is operated using the contents from the chipset attached memory while the one or more physical adjustments are made to adjust the system memory. After the one or more physical adjustments, the contents are transferred back from the chipset attached memory to the adjusted system memory via the chipset link.

Physical adjustment to system memory with chipset attached memory

Random access memory (RAM) is attached to an input/output (I/O) controller of a chipset (e.g., on a motherboard). This chipset attached RAM is optionally used as part of a tiered storage solution with other tiers including, for example, nonvolatile memory (e.g., a solid state drive (SSD)) or a hard disk drive. The chipset attached RAM is separate from the system memory, allowing the chipset attached RAM to be used to speed up access to frequently used data stored in the tiered storage solution without reducing the amount of system memory available to an operating system running on the one or more processing units.

Chipset attached random access memory

Package lids with carveouts configured for processor connection and alignment are described. Lid carveouts are configured to align and mechanically secure a cooling device to the package lid by receiving protrusions of the cooling device. Because the lid carveouts ensure precise alignment and orientation of a cooling device relative to a package lid, the lid design enables targeted cooling of discrete portions of the lid. Lid carveouts are further configured to expose one or more connectors disposed on a surface that supports package internal components. When contacted by corresponding connectors of a cooling device, the lid carveouts enable direct connections between the package and the attached cooling device. By creating a direct connection between package components and an attached cooling device, the lid carveouts enable a high-speed connection for proactive and on-demand cooling actuation.

Lid carveouts for processor connection and alignment

Core activation and deactivation for a multi-core processor is described. In accordance with the described techniques, a processor having multiple cores operates using a first core configuration. A request to switch from the first core configuration to a second core configuration is received. Responsive to the request, a switch from the first core configuration to the second core configuration occurs by adjusting a number of active cores of the processor without rebooting.

Core activation and deactivation for a multi-core processor

User configurable hardware settings for overclocking is described. In accordance with the described techniques, user input to adjust hardware settings for operating a processing unit in an overclocking mode is received. The user input, for example, adjusts at least one of a voltage droop threshold or a frequency adjustment of the clock rate. A voltage droop is detected while operating the processing unit in the overclocking mode. Responsive to detecting the voltage droop, a clock rate of the processing unit is adjusted based at least in part on the adjusted hardware settings.

User configurable hardware settings for overclocking

Automatic central processing unit (CPU) usage optimization includes: monitoring performance activity of a workload comprising a plurality of threads; and modifying a resource allocation of a plurality of cores for the plurality of threads based on the performance activity.

Automatic central processing unit (CPU) usage optimization

Profile switching for memory overclocking is described. In accordance with the described techniques, a memory is operated according to a first memory profile. During operation of the memory according to the first memory profile, a request is received to operate the memory according to a second memory profile. Responsive to the request, operation of the memory is switched to operate according to the second memory profile without rebooting. In one or more implementations, at least one of the first memory profile or the second memory profile comprises an overclocking memory profile that configures the memory to operate in an overclocking mode. In one or more implementations, the memory is trained to operate according to the overclocking memory profile prior to operating the memory according to the first memory profile.

Real time profile switching for memory overclocking

Methods and apparatuses control electrical current supplied to a plurality of processing units in a multi-processor system. A plurality of current usage information corresponding to the processing units are received by a controller to determine a threshold current for each of the processing units. The controller determines a frequency reduction action and an instructions-per-cycle (IPC) reduction action for the each of the processing units based on the threshold current and regulates operations of the processing units based on the determined frequency and IPC reduction actions.

System and method for controlling electrical current supply in a multi-processor core system via instruction per cycle reduction

Growing community of inventors

Fort Collins, CO, United States of America

Amitabh Mehra