Texas Instruments Corporation

Amitabh Jain

Mahalingam Nandakumar

Haowen Bu

Peijun Chen

Manoj Mehrotra

Brian Keith Kirkpatrick

Thomas Dyer Bonifield

Srinivasan Chakravarthi

Duofeng Yue

Sue E Crank

Homi C Mogul

Deborah J Riley

Antonio Luis Pacheco Rotondaro

Stephanie Watts Butler

Gordon P Pollack

Stanley Seungchul Song

James Joseph Chambers

Douglas Ticknor Grider

Kaiping Liu

Jorge Adrian Kittl

Song Zhao

Kwan-Yong Lim

Steven Lee Prins

Donald S Miles

Jihong Chen

Himadri Sekhar Pal

Clinton L Montgomery

Mark Stephen Rodder

Zhiqiang (Jeff) Wu

Shashank Sureshchandra Ekbote

Rick L Wise

Youn Sung Choi

Seung-Chul Song

Reima Tapani Laaksonen

Puneet Kohli

Eddie Hearl Breashears

Ebenezer Eshun

Wayne A Bather

P R Chidambaram

Lahir Shaik Adam

Suresh Potla

Xin Zhang

Chidi P R Chidambaram

Chimin Hu

A method of fabricating an integrated circuit includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric. The first dielectric material is etched to form sidewall spacers on sidewalls of the gate stack. A top surface of the first dielectric material is chemically converted to a second dielectric material by adding at least one element to provide surface converted sidewall spacers. The second dielectric material is chemically bonded across a transition region to the first dielectric material.

Integrated circuit having chemically modified spacer surface

An integrated circuit containing MOS transistors may be formed using a split carbon co-implantation. The split carbon co-implant includes an angled carbon implant and a zero-degree carbon implant that is substantially perpendicular to a top surface of the integrated circuit. The split carbon co-implant is done at the LDD and halo implant steps.

Threshold mismatch and IDDQ reduction using split carbon co-implantation

A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor.

Recessed channel insulated-gate field effect transistor with self-aligned gate and increased channel length

A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon and a halogen, and a boron specie to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode on a gate dielectric formed on the semiconductor surface. Source and drain implantation is performed to establish source/drain regions, wherein the source/drain regions are distanced from the gate structure further than the source/drain extension regions. Source/drain annealing is performed after the source and drain implantation. The co-implants can be selectively provided to only core PMOS transistors, and the method can include a ultra high temperature anneal such as a laser anneal after the PLDD implantation.

Indium, carbon and halogen doping for PMOS transistors

An integrated circuit containing an MOS transistor with epitaxial source and drain regions may be formed by implanting a retrograde anti-punch-through layer prior to etching the source drain regions for epitaxial replacement. The anti-punch-through layer is disposed between stressor tips of the epitaxial source and drain regions, and does not substantially extend into the epitaxial source and drain regions.

Drain induced barrier lowering with anti-punch-through implant

An integrated circuit having a replacement gate MOS transistor and a polysilicon resistor may be formed by removing a portion at the top surface of the polysilicon layer in the resistor area. A subsequently formed gate etch hard mask includes a MOS hard mask segment over a MOS sacrificial gate and a resistor hard mask segment over a resistor body. The resistor body is thinner than the MOS sacrificial gate. During the gate replacement process sequence, the MOS hard mask segment is removed, exposing the MOS sacrificial gate while at least a portion of the resistor hard mask segment remains over the resistor body. The MOS sacrificial gate is replaced by a replacement gate while the resistor body is not replaced.

ZTCR poly resistor in replacement gate flow

An integrated circuit (IC) includes a plurality of strained metal oxide semiconductor (MOS) devices that include a semiconductor surface having a first doping type, a gate electrode stack over a portion of the semiconductor surface, and source/drain recesses that extend into the semiconductor surface and are framed by semiconductor surface interface regions on opposing sides of the gate stack. A first epitaxial strained alloy layer (rim) is on the semiconductor surface interface regions, and is doped with the first doping type. A second epitaxial strained alloy layer is on the rim and is doped with a second doping type that is opposite to the first doping type that is used to form source/drain regions.

Strain-engineered MOSFETs having rimmed source-drain recesses

A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 &#x212b; of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate. The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.

Carbon and nitrogen doping for selected PMOS transistors on an integrated circuit

A process of integrated circuit manufacturing includes providing () a spacer on a gate stack to provide a horizontal offset over the channel region for otherwise-direct application () of a PLDD implant dose in semiconductor, additionally depositing () a seal substance to provide a screen thickness vertically while thereby augmenting the spacer on the gate stack to provide an increased offset horizontally from the gate stack and form a horizontal screen free of etch, and subsequently providing () an NLDD implant dose for NLDD formation. Various integrated circuit structures, devices, and other processes of manufacture, and processes of testing are also disclosed.

Offset screen for shallow source/drain extension implants, and processes and integrated circuits

A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.

Method of forming a CMOS device with a stressed-channel NMOS transistor and a strained-channel PMOS transistor

Carbon and nitrogen doping for selected PMOS transistor on an integrated circuit

A process for forming diffused region less than 20 nanometers deep with an average doping dose above 10cmin an IC substrate, particularly LDD region in an MOS transistor, is disclosed. Dopants are implanted into a source dielectric layer using gas cluster ion beam (GCIB) implantation, molecular ion implantation or atomic ion implantation resulting in negligible damage in the IC substrate. A spike anneal or a laser anneal diffuses the implanted dopants into the IC substrate. The inventive process may also be applied to forming source and drain (S/D) regions. One source dielectric layer may be used for forming both NLDD and PLDD regions.

Formation of shallow junctions by diffusion from a dielectronic doped by cluster or molecular ion beams

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Allen, TX, United States of America

Amitabh Jain