Symantec Corporation

Cadence Design Systems, Inc.

Amit Verma

Anindya Banerjee

David Spatafore

Suyash Kumar

Amol Manohar Vaikar

Sumesh Jaiswal

Navin Kabra

Habeeb Farah

Yumi Monma

Rajorshi Ghosh Choudhury

Devank Jain

Anubhav Srivastava

Methods and systems for providing concise data for analyzing checker completeness, in the context of formal verification analysis of circuit designs. The methods and systems concisely report information useful to a human user (e.g., circuit designer or verification engineer) for efficiently determining what manual action should be taken next to resolve holes in verification coverage. The reported information can include lists of signals on which checkers can be written, which lists can be ranked, can be limited to a subset of interest signals, and can include corresponding cover items for each reported interest signal. The present systems and methods thereby improve on reporting provided to the user, permitting the user to more quickly advance a formal verification process toward full coverage of the relevant portions of a circuit design.

Providing concise data for analyzing checker completeness

The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and automatically identifying one or more code coverage points from a netlist of an original model associated with the electronic design. Embodiments may include receiving a property and one or more elements, each of the one or more elements corresponding to one of the one or more code coverage points. Embodiments may further include performing model checking based upon, at least in part, the property and the one or more elements. Embodiments may also include verifying the property and generating an unsatisfiability core based upon, at least in part, the one or more elements.

System, method, and computer program product for improving coverage accuracy in formal verification

The present disclosure is directed towards electronic circuit design and verification. Embodiments may include receiving, using a processor, source code corresponding to at least a portion of an electronic design and generating at least one coverage model for each of a dynamic verification and a formal verification. The method may further include determining a formal data set including stimuli coverage status, cone of influence coverage status, and proof coverage status and consolidating the formal data set using a user-programmable consolidation function to generate a combined formal coverage data set.

System, method, and computer program product for computing formal coverage data compatible with dynamic verification

A computing device receives a file. The computing device determines whether the file has previously been scanned for violations of a data loss prevention policy. If the file was previously scanned, a result of the previous scan is used to decide whether or not the file violates the data loss prevention policy. If the file was not previously scanned, the file is scanned to decide whether or not the file violates the data loss prevention policy.

System and method for reducing data loss prevention scans

A computer-implemented method for data-loss prevention may include: 1) identifying data associated with a user, 2) determining that the data is subject to a data-loss-prevention scan, 3) identifying a data-loss-prevention reputation associated with the user, and then 4) performing a data-loss-prevention operation based at least in part on the data-loss-prevention reputation associated with the user. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for reputation-based application of data-loss prevention policies

A method and apparatus for preventing data leakage facilitated by steganography is provided. In one embodiment, the method for preventing data leakage caused by steganography without perceptual quality degradation comprises processing content being transmitted from a computer, wherein the content comprises steganographic data; and before the transmission, modifying the steganographic data to corrupt hidden information within the content without perceptual quality degradation.

Method and apparatus for preventing data leakage faciliated by steganography

Systems and methods described herein may separate one or more enhancement layers of a multimedia file from a base layer of the multimedia file and treat the base layer and the enhancement layer differently when backing up and/or archiving the multimedia file (e.g., by giving the enhancement layer a lower priority than the base layer). By separating enhancement layers from multimedia files and treating the enhancement layers with a lower priority, these systems and methods may reduce the strain that large multimedia files put on data repositories and associated computing resources (e.g., storage space, network bandwidth, etc.) while still preserving and protecting enough of the multimedia file to keep important information that the multimedia file may contain intact.

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Uttar Pradesh, India

Amit Verma