Dell Products Inc.

Agere Systems Inc.

Amit Shah

Vadhiraj Sankaranarayanan

David Allen Brown

Tuyet-Huong Thi Nguyen

Mark Lawrence Farley

Mark Dykstra

Hasnain Shabbir

Vijay Bharat Nijhawan

Andrew Butcher

Yuwei Cai

René Franco

Ananya Mukherjee

James R Pledge

An information handling system includes a memory controller with an error logger, and a DIMM coupled to the memory controller via a memory channel. The DIMM includes a non-volatile memory device mapped to include event blocks that store error information associated with memory events occurring the memory controller, the DIMM, and the memory channel. Each event block includes a flag field and a data field. The error logger receives an indication that a memory event has occurred, reads first flag information from a flag field of an event block, determines whether the event block is locked based upon the first flag information, and if the event block is not locked, then writes second flag information to the flag field and writes event information to a data field of the event block. The event information describes the memory event.

System and method for targeted efficient logging of memory failures

A dual in-line memory module (DIMM) thermal control system for intelligent DIMM thermal controls for maximum uptime may include a memory subsystem. The memory subsystem may include a first DIMM and a first serial presence detect (SPD) module associated with the first DIMM. The DIMM thermal control system may also include a baseboard management controller (BMC). The BMC may, when a first DIMM failure of the first DIMM may be detected, record a first failure event in a first failure events log of the first SPD module. The first failure event may comprise the first DIMM failure and associated first thermal telemetry data of the first DIMM. The BMC may also adjust DIMM thermal control settings to reduce temperature of the first DIMM based on the first failure events log including at least the first failure event.

Intelligent dual inline memory module thermal controls for maximum uptime

An information handling system includes a processor, a dual in-line memory module (DIMM), and a memory controller coupled to the DIMM. The memory controller provides interrupts to the processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor to receive the interrupts, accumulate a count of the interrupts, and provide a first error indication when the count exceeds a first error threshold. The failure predictor increments the count each time the predictor receives a particular interrupt and decrements the count in accordance with an error leak rate. The error leak rate has a first value when the DIMM is newer than a first age threshold and has a second value when the DIMM is older than the first age threshold.

System and method to control memory failure handling on double-data rate dual in-line memory modules

An information handling system for DIMM provisioning and RAS enablement may include a memory subsystem that may comprise a DIMM including a set of ranks, each rank of the set of ranks may include a set of DRAMs, each DRAM of the set of DRAMs including a set of rows, and a non-volatile memory associated with the DIMM. The DIMM may include a post package repair (PPR) history including a set of PPR history entries. Each PPR history entry of the set of PPR history entries may include a failed row count for each rank of a corresponding DRAM of the DIMM. The information handling system may also include a BIOS that may determine whether health of the DIMM is unhealthy that may be based on the PPR history. When the health of the DIMM may be unhealthy, the BIOS may also perform a PPR corrective action procedure.

Dual inline memory provisioning and reliability, availability, and serviceability enablement based on post package repair history

An information handling system includes a processor, a dual in-line memory module (DIMM), and a memory controller coupled to the DIMM. The memory controller provides interrupts to the processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor that receives the interrupts, accumulates a count of the interrupts, and provides an error indication when the count exceeds an error threshold. The failure predictor receives a first in time interrupt, suspends the accumulation of the count for a first duration of time in response to receiving the first in time interrupt, and resumes the accumulation of the count. In resuming the accumulation of the count, the failure predictor increments the count each time the predictor receives a first subsequent interrupt and decrements the count in accordance with an error leak rate.

System and method to control memory failure handling on double-data rate dual in-line memory modules via suspension of the collection of correctable read errors

A processor includes at least a portion of a first split transmit and receive media access controller (MAC), the split transmit and receive MAC having a transmit unit and a receive unit physically separated from one another. An interface for directing signals between the transmit unit and the receive unit of the first split transmit and receive MAC is configurable to multiplex the signals with other signals directed between a transmit unit and a receive unit of at least a second split transmit and receive MAC. The interface may comprise a plurality of channels, each having one or more ports associated therewith, wherein a given signal to be directed between transmit and receive units of a given split transmit and receive MAC is assigned to a particular channel and port of the interface.

Processor having split transmit and receive media access controller with reduced complexity interface

An internal memory controller of a network processor or other type of processor controls access of processor clients to memory instances of an internal memory of the processor. The internal memory controller includes a configurable switching element that is connectable between the clients and the memory instances, and is operative to control access of particular ones of the clients to particular ones of the memory instances. Generally, the configurable switching element is configurable to connect any one of at least a subset of the clients to each of at least a subset of the memory instances. In a first selectable configuration of the configurable switching element, a given one of the processor clients is permitted to access a first set of one or more memory instances, and in a second selectable configuration of the configurable switching element, the given processor client is permitted to access a second set of one or more memory instances, with the second set being different than the first set.

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Austin, TX, United States of America

Amit Shah