Nvidia Corporation

Amit Pabalkar

Steven E Molnar

Thomas Edward Dewey

Sau Yan Keith Li

Simon Lai

Ashutosh Pandey

Arthur Chen

Harold W Cain, Iii

Prabal Sharma

Santosh Nayak

Mirko Andjic

Sachin Satish Idgunji

Narayan Kulshrestha

Arvind Gopalakrishnan

Aniket Naik

Bardia Zandian

Siddharth Bhargav

Justin Tai

Various embodiments include techniques for managing cache memory in a computing system. The disclosed techniques include a cache policy manager that monitors activity of various components that access a common cache memory. The cache policy manager establishes cache rules that determine what data remains stored in cache memory and what data is removed from cache memory in order to make room for new data. As the activities of these components change over time, cache rules that work well for a previous activity profile may no longer work well for the current activity profile. Therefore, the cache policy manager dynamically modifies the cache rules as the activity profile changes in order to select cache rules at any given time that work well with the current activity profile. These techniques are advantageous over conventional approaches that employ static cache rules that work well only for specific activity profiles.

Managing a programmable cache control mapping table in a system level cache

Managing a system level cache

A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.

Power management in a multiple-processor computing device

Embodiments of the present invention provide methods and apparatus for metering GPU workload in real time. Metering of the GPU workload is performed by a Workload Metering (WLM) algorithm implemented in software or firmware that calculates a duty cycle for the graphics engine. The duty cycle forces the graphics engine to transition from a busy state to an idle state periodically based on measured power consumption, and engages race-to-sleep techniques to place the engine or engines in a low power state during the forced idle times, thereby reducing the overall power draw of the GPU to meet a predetermined power budget. According to some embodiments, the WLM algorithm is deployed on a microcontroller of a power management unit (PMU).

Metering GPU workload with real time feedback to maintain power consumption below a predetermined power budget

Integrated circuits, or computer chips, typically include multiple hardware components (e.g. memory, processors, etc.) operating under a shared power (e.g. thermal) constraint that is sourced by one or more power sources for the chip. Typically, the hardware components can be individually configured to operate at certain states (e.g. to operate at a certain frequency by setting a clock speed for a clock dedicated to the hardware component). Thus, each hardware component can be configured to operate at an operating point that is determined to be optimal, usually in terms of achieving some desired goal for a specific application (e.g. frame rates for gaming, etc.). In the context of chip hardware that operates under a shared power/thermal constraint, a method, computer readable medium, and system are provided for determining the optimal operating point for the chip that takes into consideration both performance of the chip and power consumption by the chip.

Optimal operating point estimator for hardware operating under a shared power/thermal constraint

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Fremont, CA, United States of America

Amit Pabalkar