Intel Corporation

Freescale Semiconductor,inc.

Amit Kumar Srivastava

Kenneth Foust

Asad Azam

Chenchu Punnarao Bandi

Duane G Quiet

Rajesh Bhaskar

Lakshminarayana Pappu

Enrico David Carrieri

Khang Choong Yong

Robert Milstrey

Dharmaray Nedalgi

Karthik Ns

Rao Jagannadha Rapeta

George Vergis

Mikal Hunsaker

Huimin Chen

Karthi R Vadivelu

Wil Choon Song

Boon Ping Koh

Nobuyuki Suzuki

Janusz Jurski

Parul K Sharma

Jagannadha Rao Rapeta

Prasad Bhilawadi

Jia Jun Lee

Sriram Balasubrahmanyam

Raghavendra Devappa Sharma

Jackson Chung Peng Kong

Eng Huat Goh

Aravindh V Anantaraman

Sanjay Kumar Wadhwa

Malay Trivedi

Ramnarayanan Ram Muthukaruppan

Zhenyu Zhu

Michael W Altmann

Myron Loewen

Vani Deshpande

David N Lombard

Chee Seng Leong

James Mitchell

Chih-Cheh Chen

Piotr Michael Kwidzinski

Navindra Navaratnam

Teong Guan Yew

Matthew A Schnoor

Khai Ern See

Lay Hock Khoo

Nidhi Chaudhry

Leonhard Heiss

Teong Keat Beh

Gaurav Goel

Chin Boon Tear

Anoop Kumar Upadhyay

Tim McKee

Rahul Bhatt

Siti Suhaila Mohd Yusof

Sabyasachi Mohapatra

Teong Guan T G Yew

Robert D Adler

In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.

Method, apparatus and system for dynamic control of clock signaling on a bus

An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode.

Scalable infield scan coverage for multi-chip module for functional safety mission application

In one embodiment, an apparatus includes: a first controller to couple to an interconnect to which a plurality of devices may be coupled, the first controller to communicate first information via the interconnect according to the native communication protocol; a first transceiver to drive the first information onto a first line of the interconnect; a second transceiver to drive a clock signal onto a second line of the interconnect; and a second controller to communicate second information via the interconnect. In an embodiment, the native communication protocol is a single-ended communication protocol and the second controller is to communicate the second information differentially via the interconnect. Other embodiments are described and claimed.

System, apparatus and method for tunneling and/or multiplexing via a multi-drop interconnect

In one embodiment, an apparatus includes: a peer-to-peer (P2P) control circuit to issue a P2P communication request to a bus master of a multi-drop interconnect to request authorization to send a P2P transaction to at least one slave device coupled to the multi-drop interconnect; a transmitter to transmit the P2P transaction to the at least one slave device when the bus master grants the authorization for the P2P transaction; and another transmitter to output the clock signal to the multi-drop interconnect during the P2P transaction. Other embodiments are described and claimed.

System, apparatus and method for peer-to-peer communication on a multi-drop interconnect

In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to dynamically cause the first communication line to communicate a clock signal to a first device group including one or more first devices to couple to the interconnect and dynamically cause the second communication line to communicate a data signal to the first device group when a communication is to be addressed to at least one of the one or more first devices of the first device group, such that the communication is transparent to at least another device group to couple to the interconnect. Other embodiments are described and claimed.

Method, apparatus and system for device transparent grouping of devices on a bus

In an embodiment, a host device includes: a transceiver to communicate information on an interconnect; a controller to control operation of the transceiver and to be a master for the interconnect; and a role transfer logic to cause a secondary device to be the master for the interconnect when at least a portion of the host device is to enter into a low power. Other embodiments are described and claimed.

Method, apparatus and system for role transfer functionality for a bus master

In one embodiment, an apparatus includes: a processing circuit to execute instructions; and a host controller coupled to the processing circuit to perform a key exchange with a second device to couple to the apparatus via a bus to which a plurality of devices may be coupled, and in response to a successful completion of the key exchange, enable secure communication with the second device. Other embodiments are described and claimed.

System, apparatus and method for secure communication on a bus

The disclosed embodiments relate to methods, systems and apparatus for dynamic temperature aware functional safety. The disclosed embodiments provide adaptive techniques to track extended dynamic temperature range of a System-on-Chip (SOC) and automatically tune critical IP components of the SOC so that system can operate reliably even at high temperatures. The disclosed embodiments relax the overdesign of the SOC components by reusing existing components such as a ring oscillator to determine temperature at different regions of the SOC. In one embodiment, the disclosed principles use a Calibrated Ring Oscillator (CRO) temperature sensors. The CRO-based temperature sensors provide fast temperature measurement suitable for detecting dynamic temperature ranges and temperature rate of change. The CROs are existing on the SOC and do not require addition of additional sensors.

Methods, systems and apparatus for dynamic temperature aware functional safety

In one embodiment, an apparatus includes an input/output (I/O) circuit to communicate information at a selected voltage via an interconnect to which a plurality of devices may be coupled, and a host controller to couple to the interconnect. The host controller may include a supply voltage policy control circuit to initiate a supply voltage policy exchange with a first device to obtain a first supply voltage capability of the first device and to cause the I/O circuit and the first device to be configured to communicate via the interconnect at a first supply voltage based on the first supply voltage capability. Other embodiments are described and claimed.

Method, apparatus and system for power supply policy exchange on a bus

In one embodiment, an apparatus includes: an accelerator to execute instructions; an accelerator request decoder coupled to the accelerator to perform a first level decode of requests from the accelerator and direct the requests based on the first level decode, the accelerator request decoder including a memory map to identify a first address range associated with a local memory and a second address range associated with a system memory; and a non-coherent request router coupled to the accelerator request decoder to receive non-coherent requests from the accelerator request decoder and perform a second level decode of the non-coherent requests, the non-coherent request router to route first non-coherent requests to a sideband router of the first die and to direct second non-coherent requests to a computing die. Other embodiments are described and claimed.

System, apparatus and method for providing a fabric for an accelerator

Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (IC) out-of-band interrupt (OBI) received on a general purpose input-output (GPIO) pin from an IC device that is unable to generate an improved inter-integrated circuit (I3C) bus an I3C in-band interrupt (IBI). The processing circuitry may further generate, based on the IC OBI, an I3C IBI that includes information related to the IC OBI. The host controller may further include transmission circuitry to transmit the I3C IBI on an I3C bus. Other embodiments may be described and/or claimed.

Out-of-band interrupt mapping in MIPI improved inter-integrated circuit communication

In an embodiment, a host controller is to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto the interconnect according to a bus clock signal; a first receiver to receive second information from at least one of the plurality of devices via the interconnect according to the bus clock signal; and a clock generation circuit to generate the bus clock signal having an asymmetric duty cycle. Other embodiments are described and claimed.

System, apparatus and method for controlling duty cycle of a clock signal for a multi-drop interconnect

In one embodiment, an apparatus includes a host controller to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto a first line of the interconnect; a second driver to drive a clock signal onto a second line of the interconnect; and a mode control circuit to cause the second driver to drive the clock signal onto the second line of the interconnect in a first mode and to cause the first driver and the second driver to drive differential information onto the first line and the second line of the interconnect in a second mode. Other embodiments are described and claimed.

System, apparatus and method for extended communication modes for a multi-drop interconnect

Methods and apparatus relating to functional safety critical audio system for autonomous and industrial applications are described. In an embodiment, safety island logic circuitry transmits an enable signal to cause initiation of a functional safety test for an audio component in a vehicle. Audio processing logic circuitry receives the enable signal and causes activation of power amplifier logic circuitry, in response to the enable signal, to drive the audio component in accordance with an audio alert test signal. The audio component includes a Parametric Acoustic Array (PAA) transducer. Other embodiments are also disclosed and claimed.

Functional safety critical audio system for autonomous and industrial applications

In one embodiment, a flash sharing controller is to enable a plurality of components of a platform to share a flash memory. The flash sharing controller may include: a flash sharing class layer including a configuration controller to configure the plurality of components to be flash master devices and configure a flash sharing slave device for the flash memory; and a physical layer coupled to the flash sharing class layer to communicate with the plurality of components via a bus. Other embodiments are described and claimed.

System, apparatus and method for sharing a flash device among multiple masters of a computing platform

Growing community of inventors

Penang, Malaysia

Amit Kumar Srivastava