International Business Machines Corporation

Amit Kumar Sarkhel

Mark Vincent Pierson

Ajit Kumar Trivedi

John Gillette Davis

Christian Robert Le Coz

Alan Harris Crudo

Charles Gerard Woychik

Kishor V Desai

Ping Kwong Seto

Bao-Tong Ma

Lawrence H White

Sudipta Kumar Ray

Anilkumar Chinuprasad Bhatt

Miguel Angel Jimarez

John Joseph Konrad

Edmond Otto Fey

Timothy Leroy Wells

Andrew Michael Seman

Jeffrey McKeveny

Kevin Taylor Knadle

Joseph Alphonse Kotylo

Edward Lee Arrington

Jose A Rios

Voya Rista Markovich

Donald Seton Farquhar

Mario John Interrante

Douglas Oliver Powell

Elizabeth F Foster

William Edward Sablinski

Brian Eugene Curcio

Brenda Lee Peterson

A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.

Method of fabricating printed circuit board with mixed metallurgy pads

A method and structure for solderably coupling an electronic module (e.g. a ceramic or plastic ball grid array module) to a circuit board. A lead-free solder ball is soldered to the module without using a joining solder to effectuate the soldering. The solder ball comprises a tin-antimony alloy that includes about 3% to about 15% antimony by weight. The solder ball is soldered to the circuit board with a lead-free joiner solder. The joiner solder comprises a tin-silver-copper alloy that includes by weight about 95.5-96.0% tin, about 3.5-4.0% silver, and about 0.5-1.0% copper. The resultant solder connection between the module and the circuit board has a fatigue life of at least about 90% of a fatigue life of a reference structure. The reference structure has a 90Pb/10Sn solder ball joined to both the module and the circuit card by a 63Sn/37Pb joiner solder.

Lead-free solder structure and method for high fatigue life

Deterioration and damage to insulator materials in an interconnection structure having vertical connections due to exposure to heat during bonding of lamina is avoided by performing diffusion bonding of metal pads at plated through holes (PTH) at temperatures below the melting points of conductive material in the bond. Diffusion bonding is achieved during time periods required for processing (e.g. curing or drying) of insulating materials in the laminated structure.

Method of forming metallic z-interconnects for laminate chip packages and boards

Printed circuit board with mixed metallurgy pads and method of fabrication

A method and structure for forming an electronic package with an interconnect structure that comprises lead-free solders. The method first forms a module by initially providing a chip carrier, a first joiner solder that is lead-free, and a core interconnect (e.g., solder ball, solder column) that includes a lead-free core solder. The liquidus temperature T of the first joiner solder is less than a solidus temperature T of the core solder. A first end of the core interconnect is soldered to the chip carrier with the first joiner solder, which includes reflowing the first joiner solder at a reflow temperature that is above T and below T , followed by cooling the first joiner solder to a temperature that is below a solidus temperature of the first joiner solder. Thus, the module with the soldered core interconnect has been formed. The method then provides a circuit card and a second joiner solder that is lead-free. The liquidus temperature T of the second joiner solder is less than T . A second end of the core interconnect is soldered to the circuit card with the second joiner solder, which includes reflowing the second joiner solder at a reflow temperature that is above T and below T , followed by cooling the second joiner solder to a lower temperature that is below a solidus temperature of the second joiner solder.

Electronic package interconnect structure comprising lead-free solders

Where an electrical connection is needed between an electric circuit on a substrate and a component with very finely spaced leads, pads are formed on the substrate at points where such connections to the circuit are to be made. A solder paste is deposited using a particular, described stencil having a thickness and apertures with specific tolerances. The component is positioned so that its leads to be attached are contiguous with corresponding pads, and the electrical connections are completed by reflowing the solder paste forming consistent and reliable electrical joints of solder alloy.

Method for producing circuit board assemblies using surface mount components with finely spaced leads

The present invention provides an integrated semiconductor module comprising a chip, interposer, and substrate. The module is adapted to be mounted on a traditional circuit card carrying multiple other components. The chip of the present invention can be a conventional IC chip or chip package, including ball grid array packages, and will simply be referred to hereinafter as a &ldquo;chip.&rdquo; The interposer of the present invention is a conventional thin film interposer, such as those composed of a polyimide material and fabricated on a glass carrier plate. The substrate of the present invention is a conventional circuitized substrate, such as a BGA or laminate substrate, that is commonly employed in carrying a chip on a circuit card. In its assembled state, the present invention comprises an interposer mounted on top of a substrate with the electrical contacts formed on the lower surface of the interposer positioned in electrical communication with respective ones of electrical contacts formed on the upper surface of the substrate. A non-conductive material, such as an epoxy resin, fills the voids between the interposer and substrate created by the electrical connections. The epoxy resin forms a mechanical bond between the interposer and substrate, thereby enhancing the structural integrity of the unit. Moreover, by filling the voids between the electrical connections, essentially no foreign particles can become entrapped therein and cause electrical malfunctions. Accordingly, the environmental and operational integrity of the unit is also enhanced.

Integrated semiconductor package

A method and apparatus for efficiently repairing or reworking a printed circuit board having a solder ball grid array thereon efficiently and at minimum cost includes the steps of drilling out a plated-through hole to sever electrical connections between a ball grid array pad on one surface of the printed circuit board and internal circuits and circuits on an opposite surface of the printed circuit board; inserting a pin having an insulated sleeve surrounding a portion thereof into the drilled-out hole, the pin having attached to one end a wire for attachment to the ball grid array on one surface of the printed circuit board and a post at the other end of the pin for attachment of a wire to the post; the pin having a stop along its length to control vertical positioning of the pin in the drilled-out hole, the pin referred to as a via replacement (VR) pin. Alternately, after the plated through hole is drilled out, an insulated wire may be inserted into the hole with insulation removed from the length of the wire which extends beyond one surface of the printed circuit board. The bare length of wire is bent parallel to the surface of the printed circuit board and attached thereto by a solder reflow process. In a dog bone configuration, the wire is formed around a pad on the surface of the printed circuit board which receives the solder ball.

Apparatus and method for printed circuit board repair

The present invention relates generally to a new semiconductor chip carrier connections, where the chip carrier and the second level assembly are made by a surface mount technology. More particularly, the invention encompasses surface mount technologies, such as, Ball Grid Array (BGA), Column Grid Array (CGA), to name a few, where the surface mount technology comprises essentially of a non-solder metallic connection, such as, a copper connection. The present invention is also related to Column Grid Array structures and process thereof.

High density column grid array connections and method thereof

Apparatus for printed circuit board repair

An adhesion pad for adhering a semiconductor chip or a ball grid array module to a supporting substrate includes a stepped or tapered structure. The structure is composed of at least one solder wettable metal or alloy layer having solder deposited thereon. The stepped or tapered structure prevents a fatigue crack from propagating in the X-Y plane above the adhesion pad.

Substrate structure for improving attachment reliability of semiconductor chips and modules

Method for improving attachment reliability of semiconductor chips and modules

Growing community of inventors

Endicott, NY, United States of America

Amit Kumar Sarkhel