Cadence Design Systems, Inc.

Achronix Semiconductor Corporation

Agnity Healthcare, Inc.

Ciena Corporation

Secretary, Department of Biotechnology

General Electric Technology Gmbh

Amit Kumar

Oleg Levitsky

Sushobhit Singh

Hansel Desmond Dsilva

Arnold Ginetti

Sanjeev Chawla

Atul Varshneya

Sasikala J

Chayan Majumder

Hitesh Marwah

Chandra Prakash Manglani

Radnya Anant Mukhedkar

Abhishek Jain

Akash Khandelwal

Sumit Arora

Ayesha Chaudhary

Dinesh Kumar

Magdalena Charbonneau

Sahaj Ghose

Sobeer Kant Jain

Gearoid Sean O'Heidhin

Avijit Bansal

Gearoid Oheidhin

Disclosed is an improved approach to implement electronic designs by performing altitude-based re-layering for I/Os. The altitude-based die stack layers allows N number of die stack layers corresponding to the actual altitudes of the I/Os in the design.

Method and system to implement altitude based I/O re-layering for electronic and photonic designs

Multiple designs for a multi-layer circuit may be simulated to determine impedance profiles of each design, allowing a circuit designer to select a design based on the impedance profiles. One feature that can be modified is the structure surrounding the barrels of a differential VIA on layers that are not connected to the differential VIA. Specifically, one antipad can be used that surrounds both barrels or two antipads can be used, with one antipad for each barrel. Additionally, the size of the antipad or antipads can be modified. These modifications affect the impedance of the differential VIA. Additionally, a conductive region may be placed that connects to the VIA barrel even though the circuit on the layer does not connect to the VIA. This unused pad, surrounded by a non-conductive region, also affects the impedance of the differential VIA.

Capacitive compensation for vertical interconnect accesses

Systems and methods include obtaining a catalog for a 'to' software release and details of a controller of a network element operating a 'from' software release, wherein the software releases are associated with the network element, and wherein the controller has a file system associated therewith; determining a delivery technique for a software load of the &#x201c;to&#x201d; software release based on the catalog and the details of the controller; and causing delivery of the software load to the file system based on the determined delivery technique, wherein the causing is one of automatic and subsequent to a user command. The delivery technique can be one of i) a full delivery, including all files in the catalog, ii) a minimal delivery, including only files in the catalog needed based on modules present in the network element, and iii) a hybrid delivery, between the full and minimal delivery.

Optimal software load delivery systems and methods to network elements

An S-parameter of a reference impedance is determined and converted to a desired mode of operation. Example modes of operation include a single-ended input output mode, a differential input output mode, and a common input output mode. The complex values of the impedance at each port as a function of frequency can be computed using the novel closed-form quadratic S-parameter equation which utilizes the concept of matched networks by setting the reflections and re-reflections to zero through S-parameter renormalization. Using the S-parameter renormalization, the insertion loss corresponding to zero reflections and re-reflections is calculated. Based on the determination of the matching impedance used to reduce the reflections and re-reflections to zero, a parameter of a circuit comprising the network may be modified to reduce noise.

Noise-independent loss characterization of networks

The invention relates to an ergonomic foot pedal and to apparatuses for manual ventilation. In an embodiment, the invention provides a compact and integrated foot pedal that enables a care provider to provide positive pressure ventilation to a subject's airways and lungs, and to optionally apply suction for the purpose of aspirating mucous, secretions, meconium, blood, fluids or other such materials from a patient&#x2014;specifically from airways.

Foot pedal

Disclosed are techniques for implementing three-dimensional or multi-layer integrated circuit designs. These techniques identify an electronic design and a plurality of inputs for implementing connectivity for the electronic design. Net distribution results may be generated at least by performing one or more net distribution analyzes. A bump in a bump array may then be assigned to a net that connects a first layer and a second layer in the electronic design based in part or in whole upon the net distribution analysis results.

Methods, systems, and computer program product for implementing three-dimensional integrated circuit designs

A method and system are provided for collaboration for sharing patient records on low computing resources on communication devices. The method includes accessing one or more patient data records via a server, where the one or more patient data records are accessed at a first communication device. The method further includes invoking a communication session with one or more second communication devices, where the communication session includes context information of the one or more patient data records. Further, the method includes sending a request to the server, by at least one of the one or more second communication devices, to access the one or more patient data records, where the request includes the context information. Finally, the method includes receiving, at the at least one of the one or more second communication devices, access to the patient data records, where the access is provided during the communication session.

Method and system for collaboration for sharing patient records on low computing resources on communication devices

A method and system are provided for co-browsing of patient records on communication devices. The method includes setting up a communication session between a first communication device and one or more second communication devices, where the communication session is initiated by the first communication device. Further, the method includes accessing one or more patient records via a server, where the one or more patient records are accessed at the first communication device. The method further includes sending a reference of the one or more patient records to the one or more second communication devices, where the reference is sent from the first communication device.

Method and system for secure co-browsing of patient records on communication devices

Various embodiments use connectivity information or model(s), design attribute(s), and system intelligence layer(s) to make lower blocks at lower levels aware of changes made in other blocks at same or different levels to implement the design at different levels synchronously. Budgeting is performed for the design to distribute budgets to respective blocks in the design. The various budgets may be borrowed from one or more blocks and lent to a block in order for this block to meet closure requirements such that a total number of iterations of the reassembly process, which integrates lower level blocks into top level design, may be reduced or completely eliminated. The design attribute(s) or the connectivity model(s) or information is updated upon the identification of changes to provide the latest information or data for properly closing a design.

Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs

In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a plurality of top level timing constraints and a description of the integrated circuit design defining a hierarchy of partitions having multiple levels with one or more nested partitions; generating timing models for each partition of the plurality of partitions in response to the description of the integrated circuit design; and concurrently generating timing budgets level by level for all partitions at each level, beginning with the lowest level to each next upper level of the hierarchy of the partitions in response to the description of the integrated circuit design, the timing models, and the plurality of top level timing constraints. Please see the detailed description and claims for other embodiments that are respectively disclosed and claimed.

Timing budgeting of nested partitions for hierarchical integrated circuit designs

A method of timing analysis of an integrated circuit (IC) design with a partition block including an original clock signal with a pair of clock paths having an external common point outside the block boundary is disclosed, including receiving a netlist of the partition block of a hierarchical IC design, analyzing a pair of clock paths having the external common point to determine first and second clock ports at the boundary of the partition block; and for the first and second clock ports, creating launch and capture clocks, making exclusive clock groups of the launch clock and the capture clock for opposing clock ports to avoid the launch and capture clocks for each port affecting other internal data paths within the partition block, and associating common path pessimism removal information with a source latency of the capture clock to adjust timing at an end point of the internal data path.

Growing community of inventors

Noida, India

Amit Kumar