Intel Corporation

Arizona State University

International Business Machines Corporation

Peregrine Power, LLC

Amit Kumar Jain

Sameer Shekhar

Chin Lee Kuan

Jonathan P Douglas

Kaladhar Radhakrishnan

Dong-Ho Han

Anant S Deval

Michael Zelikson

Kevin Joseph Doran

Rajapandian Ayyanar

Bok Eng Cheah

Jackson Chung Peng Kong

Fabrice Paillet

Mark Charles Carbone

Chee Lim Nge

Alexander Lyakhov

Sergio Carlo Rodriguez

Nimrod Angel

Stuart A Friedberg

Ravi Sankar Vunnam

Sunil K Nagarajrao

Alexander Waizman

Merwin M Brown

Vivek Saxena

Pooja Nukala

Xiaolin Mao

Sunil J Unadkat

Mauricio Aguilar Salas

An apparatus, system, and method for improved thermal design power (TDP) range are provided. A device includes a first voltage regulator configured to provide first voltage of a first voltage value, a second voltage regulator configured to provide a second voltage of a second, different voltage value, a first capacitor electrically coupled between a first output of the first voltage regulator and a ground, a second capacitor electrically coupled between a second output of the second voltage regulator and the ground, a first switch electrically coupled between the first output and the second output, a second switch situated in parallel with the first switch, the second switch electrically coupled between the first output and the second output, and a controller configured to provide control signals that control the first voltage regulator, the second voltage regulator, the first switch, and the second switch.

Platform voltage regulator circuitry configurations

Techniques and mechanisms for determining an operational mode of a voltage regulator. In an embodiment, an integrated circuit (IC) die is coupled to receive power from a voltage regulator (VR) via a power delivery network (PDN) which comprises circuitry in or on a substrate, such as that of a printed circuit board. The IC die receives from the substrate information indicating a characteristic of a parasitic impedance at the substrate. Based on the information, a controller unit at the IC die selects one of multiple VR modes which each correspond to a respective one of different parasitic impedance characteristics. The controller then signals the VR to provide the selected mode. In an embodiment one of the VR modes corresponds to a relatively high impedance, and also corresponds to a relatively stable sensitivity function in a frequency range above a control bandwidth.

Device, method and system to determine a mode of voltage regulation based on parasitics of a power delivery network

Embodiments disclosed herein include electronic packages and their components. In an embodiment, an electronic package comprises a package substrate and a base die over the package substrate. In an embodiment, the electronic package further comprises a plurality of chiplets over the base die. In an embodiment, the base die comprises a substrate, a first metal layer and a second metal layer between the substrate and the plurality of chiplets, and a third metal layer and a fourth metal layer between the package substrate and the substrate. In an embodiment, a filter is integrated into one or more layers of the base die.

EM and RF mitigation silicon structures in stacked die microprocessors for die to platform and die-die RF noise suppression

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.

Embedded bridge substrate having an integral device

According to various examples, a stacked semiconductor package is described. The stacked semiconductor package may include a package substrate. The stacked semiconductor package may also include a base die disposed on and electrically coupled to the package substrate. The stacked semiconductor package may further include a mold portion disposed on the package substrate at a periphery of the base die, the mold portion may include a through-mold interconnect electrically coupled to the package substrate. The stacked semiconductor package may further include a semiconductor device having a first section disposed on the base die and a second section disposed on the mold portion, wherein the second section of the semiconductor device may be electrically coupled to the package substrate through the through-mold interconnect.

Stacked semiconductor package and method of forming the same

Various embodiments provide a magnetic sensing scheme for a voltage regulator circuit. The voltage regulator circuit may include a first inductor (also referred to as an output inductor) coupled between a drive circuit and an output node. The voltage regulator circuit may further include a second inductor (also referred to as a sense inductor) having a first terminal coupled to the first inductor at a tap point between terminals of the first inductor. The second inductor may provide a sense voltage at a second terminal of the second inductor. A control circuit may control a state of the voltage regulator circuit based on the sense voltage to provide a regulated output voltage at the output node. Other embodiments may be described and claimed.

Magnetic sensing scheme for voltage regulator circuit

Embodiments disclosed herein include electronics packages with improved thermal pathways. In an embodiment, an electronics package includes a package substrate. In an embodiment, the package substrate comprises a plurality of backside layers, a plurality of front-side layers, and a core layer between the plurality of backside layers and the plurality of front-side layers. In an embodiment, an inductor is embedded in the plurality of backside layers. In an embodiment, a plurality of bumps are formed over the front-side layers and thermally coupled to the inductor. In an embodiment, the plurality of bumps are thermally coupled to the core layer by a plurality of vias.

Structures to facilitate heat transfer within package layers to thermal heat sink and motherboard

Described is an apparatus and method to prevent a processor from abruptly shutting down by proactive power management. The apparatus comprises a power supply rail to receive a current and a voltage from a power supply generator (e.g., a DC-DC converter, and low dropout regulator); a processor coupled to the power supply rail, wherein the processor is to operate with a current and a voltage provided by the power supply rail; and an interface to receive a request to throttle one or more performance parameters of the processor when a monitored current through the power supply rail or a monitored voltage on the power supply rail crosses a threshold current or a threshold voltage, respectively, wherein the threshold current is below a catastrophic threshold current of a voltage regulator, or wherein the threshold voltage is above a catastrophic threshold voltage of the processor.

Apparatus and method for proactive power management to avoid unintentional processor shutdown

Embodiments herein relate to a package having a substrate with a core layer with a plurality of conductors coupling a first side of the core layer with a second side of the core layer, and a shield within the core layer that separates a first conductor of the plurality of conductors from a second conductor of the plurality of conductors where the shield is to reduce electromagnetic interference received by the second conductor that is generated by the first conductor. Embodiments may also be related to a package having a substrate with a through hole via through the substrate, where an EMI protective material is applied to a surface of the substrate that forms the via to shield an inner portion of the via.

Shield to protect vias from electromagnetic interference

An apparatus is provided which comprises: a first voltage regulator; a second voltage regulator; and a switch to selectively couple the first voltage regulator to the second voltage regulator, such that a first output node of the first voltage regulator is temporarily coupled to a second output node of the second voltage regulator via the switch.

Apparatus, system, and method for reducing voltage overshoot in voltage regulators

Particular embodiments described herein provide for an electronic device that can be configured to include a plurality of chiplets, a plurality of resources, a system thermal engine, and at least one processor. The at least one processor is configured to cause the system thermal engine to monitor the plurality of chiplets, where the plurality of chiplets are part of a multi-chip module, determine that a first chiplet from the plurality of chiplets has reached a threshold temperature, and reduce power to the first chiplet without reducing power to the other chiplets in the plurality of chiplets.

Per chiplet thermal control in a disaggregated multi-chiplet system

Some embodiments include apparatuses having a switching circuit included in a buck converter; an output node; an inductor including a first portion having a first terminal coupled to the switching circuit, a second portion having a second terminal coupled to the output node, and a third terminal between the first and second portions; and a capacitor coupled to the second terminal, the second terminal to couple to a first additional capacitor, and the third terminal to couple to a second additional capacitor.

Multi-terminal inductors for voltage regulators

Described is an apparatus which comprises: a power supply node; a plurality of inductors inductively coupled with one another, wherein at least one inductor of the plurality is electrically coupled to the power supply node; a plurality of loads; and a plurality of capacitors coupled to the plurality of inductors, respectively, and also coupled to the plurality of loads, respectively.

Noise mitigation apparatus and method with positively and negatively coupled inductors

Techniques and mechanisms for mitigating an overshoot of a supply voltage provided with a voltage regulator (VR). In an embodiment, buck converter functionality of a VR is provided with first circuitry comprising a first inductor and first switch circuits variously coupled thereto. Second circuitry of the VR comprises a second inductor and second switch circuits variously coupled thereto. In response to an indication of a voltage overshoot condition, respective states of the first switch circuits and the second switch circuits are configured to enable a conductive path for dissipating energy with the first inductor, the second inductor, and various ones of the first switch circuits and the second switch circuits. In another embodiment, mitigating the voltage overshoot condition comprises alternately toggling between two different configurations of the second switch circuits.

Growing community of inventors

Portland, OR, United States of America

Amit Kumar Jain