Qualcomm Incorporated

Apple Inc.

Salesforce Com, Inc.

Avago Technologies International Sales Pte. Limited

Salesforce, Inc.

Amit Kumar

Vedaraman Geetha

Keith Robert Pflederer

Ramkumar Srinivasan

Lingtao Zhang

Chang Lu

Vikas Kumar Sinha

Puneet Agarwal

William Brad Matthews

Bruce Hui Kwan

Ian D Kountanis

Muawya M Al-Otoom

Brian Robert Mestan

Mridul Agarwal

Conrado Blasco

Nikhil Gupta

Douglas C Holman

Haoyan Jia

Suchindra Rengan

Sybil Shim

Tushar G Jadhav

A reservation station that includes primary and secondary storage circuits is disclosed. The primary storage circuit may include multiple full entries, while the secondary storage circuit includes multiple store-data entries. A given store-data entry of the multiple store-data entries stores a subset of the information stored in a given full entry of the multiple full entries. In response to a determination that a store address associated with a particular store operation, stored in particular full entry of the multiple full entries, has been available for use for a threshold number of cycles without store data associated with the particular store operation being available for use, a control circuit may transfer the particular store operation to a particular store-data entry of the multiple store-data entries.

Reservation station with primary and secondary storage circuits for store operations

Resources of an electronic device are partitioned into a plurality of resource portions to be utilized by a plurality of clients. Each resource portion is assigned to a respective client, has a respective partition identifier (ID), and corresponds to a plurality memory bandwidth usage states tracked for a plurality of memory blocks. For each resource portion, each of the memory bandwidth usage states is associated with a respective memory block and indicates at least how much of a memory access bandwidth assigned to the respective partition ID to access the respective memory block is used. A usage level is determined for each resource partition based on the memory bandwidth usage states, and applied to adjust a credit count. When the credit count is adjusted beyond a request issue threshold, a next data access request is issued from a memory access request queue for the respective partition ID.

Methods and systems for memory bandwidth control

A method to provide multi-objective recommendations. The method includes receiving user input indicating a plurality of objectives, where each of the plurality of objectives indicates a desired goal for a field of interest, receiving user input indicating a plurality of actionable fields, receiving user input indicating selection of one of a plurality of records in a data set, determining, based on applying an evolutionary algorithm, one or more candidate changes to values of the plurality of actionable fields of the selected record, determining, for each of the one or more candidate changes, a multi-objective score for that candidate change, selecting one or more of the one or more candidate changes to recommend to a user based on the multi-objective scores of the one or more candidate changes, and providing, for display to the user, the selected one or more candidate changes as recommended changes.

Multi-objective recommendations in a data analytics system

Resources of an electronic device are partitioned into a plurality of resource portions to be utilized by a plurality of clients. Each resource portion is assigned to a respective client, has a respective partition identifier (ID), and corresponds to a plurality of memory bandwidth usage states tracked for a plurality of memory blocks. For each resource portion, each of the memory bandwidth usage states is associated with a respective memory block and indicates at least how much of a memory access bandwidth assigned to the respective partition ID to access the respective memory block is used. A usage level is determined for each resource partition based on the memory bandwidth usage states, and applied to adjust a credit count. When the credit count is adjusted beyond a request issue threshold, a next data access request is issued from a memory access request queue for the respective partition ID.

Techniques are disclosed relating to signature-based instruction prefetching. In some embodiments, processor pipeline circuitry executes a computer program that includes control transfer instructions, such that the execution follows a taken path through the computer program. First signature prefetch table circuitry indicates prefetch addresses for signatures generated using a first signature generation technique and second signature prefetch table circuitry indicates prefetch addresses for signatures generated using a second, different signature generation technique. Signature prefetch circuitry, in response to a prefetch training event, determines a first signature according to the first technique and a second signature according to the second technique and selects one but not both of the first and second signature prefetch tables to train using the first signature or the second signature.

Multi-table signature prefetch

In an embodiment, an indirect branch predictor generates indirect branch predictions based on one or more register values. The register values may be the contents of registers on which the indirect branch instruction is directly or indirectly dependent for generating the branch target address, for example. In an embodiment, at least one of the registers may be a source for a load instruction, and the indirect branch may be dependent (directly or indirectly) on the target of the load. In an embodiment, the indirect branch predictor may be one of at least two indirect branch predictors in a processor. The other indirect branch predictor may be based on a fetch address, or PC, associated with the indirect branch instruction. The other indirect branch predictor may generate a first predicted target address, and the indirect branch predictor may generate a second predicted target address for the same indirect branch instruction.

Indirect branch predictor based on register operands

Examples are described herein that relate to determining a level of relatedness between datasets. An approximation can be made of whether an entry in a first dataset appears in a same row as an entry in a second dataset. The approximation can be made by grouping entries in the second dataset together and determining an occurrence that an entry occurs in a same row as any of the entries in a grouping of entries. A test of independence between datasets can be made based at least on the occurrence values. Datasets can be ranked according to level of independence and presented to a user as candidates to join with a dataset. Occurrence values or rankings can be precomputed and available for use so that join candidates can be presented with a little amount of perceived delay to a user. A user interface can present join candidates for a dataset and allow the user the select datasets for joining. Joining of first and second datasets can supplement entries in both of the datasets and create a third dataset.

Techniques for determining and presenting dataset join candidates

System and methods are described for improving automated data discovery analysis in a cloud computing environment. A method includes receiving a request to analyze a data set stored in the memory device, the data set including one or more columns, the one or more columns including one or more data values in one or more cells of each column; classify each of the one or more columns as a type of column; for a selected one of the one or more columns, if the selected column's type is an external type, join one or more columns of an external knowledge base correlated to the selected column into the data set to create an expanded data set; and execute an automated data discovery model on the expanded data set.

Automated data discovery with external knowledge bases

A distributed switch architecture supports very high bandwidth applications. For instance, the distributed switch architecture may be implemented for cloud networks. The architecture scales by organizing traffic management components into tiled structures with distributed buffering. The tile structures are replicated and interconnected to perform transfers from ingress to egress using an interconnect bandwidth scheduling algorithm. Bandwidth scaling may be achieved by adding more tiles to achieve higher bandwidth. The interconnect in the architecture may be swapped out depending on implementation parameters, e.g., physical efficiency.

Distributed switch architecture

Techniques are disclosed relating to diagnosing a network-accessible device. A first computer may store authorization information associated with a plurality of network-accessible computing devices associated with a user. The first computer system may receive, from a second computer system, a request from the user to perform a diagnostic operation that involves communication between a third computer system and a particular one of the plurality of network-accessible computing devices. The first computer system may request, based on a permission indicated by the stored authorization information, that the third computer system retrieve diagnostic information from the particular network-accessible computing device and perform the diagnostic operation. The first computer system may receive, from the third computer system, result information relating to the diagnostic operation.

Growing community of inventors

Fremont, CA, United States of America

Amit Kumar