Texas Instruments Corporation

Other

Amit Kumar Gupta

Peng Cao

Karthikeyan Soundarapandian

Venkata Krishnan Kidambi Srinivasan

Prashant Prahlad

Onur Filiz

Archana Srikanta

Song Hu

Krishnasawamy Nagaraj

Vijayakumar Dhanasekaran

Venkatesh Acharya

An ADC includes a comparator to provide a comparator output responsive to an input voltage of the ADC and a DAC output voltage; a SAR circuit including a SAR that stores an n-bit digital code that is initialized at a beginning of a conversion phase of the ADC, where the SAR circuit is to update the digital code responsive to the comparator output, where an ADC output is responsive to the digital code at an end of the conversion phase; and a DAC to provide the DAC output voltage responsive to the digital code and a reference voltage. The DAC includes an m-bit CDAC and an (n−m)-bit RDAC to provide an intermediate voltage responsive to the n−m least-significant bits of the digital code and the reference voltage. The CDAC provides the DAC output voltage responsive to the m most-significant bits of the digital code, the intermediate voltage, and reference voltage.

Oversampled analog to digital converter

The present application relates to performing a scale-down of the computing resources allocated to executing a software application. For example, the software application for implementing a web server may be packaged as a container image, and one or more instances of the container images may be executed as one or more tasks. The individual tasks may be allocated a set of computing resources such as CPU and memory, and the incoming requests sent to the web server may be distributed across the tasks. If the volume of incoming requests drops below a threshold level, one or more of the tasks may be placed in standby mode, and the amount of computing resources allocated to such tasks may be reduced. When the volume of incoming requests returns above the threshold level, the amount of computing resources allocated to such tasks can be scaled back up to the full amount.

Scaling down computing resource allocations for execution of containerized applications

The present application relates to performing a scale-up of the computing resources allocated to executing a software application. For example, the software application for implementing a web server may be packaged as a container image, and one or more instances of the container images may be executed as one or more tasks. The individual tasks may be allocated a set of computing resources such as CPU and memory, and the incoming requests sent to the web server may be distributed across the tasks. If the volume of incoming requests drops below a threshold level, one or more of the tasks may be placed in standby mode, and the amount of computing resources allocated to such tasks may be reduced. When the volume of incoming requests returns above the threshold level, the amount of computing resources allocated to such tasks can be scaled back up to the full amount.

Scaling up computing resource allocations for execution of containerized applications

A delta-sigma modulator includes a first amplifier having an input, a feedback control input, and an output. The input is a first input of the delta-sigma modulator. The delta-sigma modulator further includes a first integrator and a first quantizer. The first integrator has an input and an output. The output of the first amplifier is coupled to the input of the first integrator. The first quantizer has an input and an output. The output of the first quantizer is coupled to the feedback control input of the first amplifier.

Delta sigma modulator

A precharge circuit comprises a gain amplifier, a comparator, a reservoir capacitor, a switch, a current source, and a switching network. The gain amplifier has a gain Gand receives an input voltage Vrefp. The gain amplifier outputs an amplified voltage GVrefp to the comparator, which compares GVrefp to a voltage across the reservoir capacitor. The comparator outputs a control signal for the switch based on the comparison. The switch couples the current source to the reservoir capacitor. The current from the current source charges the reservoir capacitor. The switching network couples the reservoir capacitor to an output of the precharge circuit during a first operating mode and provides the input voltage Vrefp to the output during a second operating mode.

Reference precharge system

A delta-sigma modulator architecture with idle tone suppression based on injecting an out-of-band signal includes: modulator input circuitry to provide a modulator input signal; modulator loop circuitry to quantize the modulator input signal to generate a modulator output signal at an oversampling frequency, and to provide a feedback signal. Digital filtering circuitry filters the modulator output signal to provide a digital output signal at a data rate frequency related to the oversampling frequency by a defined oversampling ratio. Out-of-band (OoB) signal generator circuitry injects a deterministic OoB injection signal at a defined OoB frequency outside of a target frequency band. The modulator input circuitry combines the analog input signal, the feedback signal, and the OoB injection signal into the modulator input signal. The digital filtering circuitry filters the OoB injection signal. The OoB injection signal can be selectively defined to suppress idle tones generated in the modulator loop circuitry.

Suppressing idle tones in a delta-sigma modulator

An analog-to-digital converter (ADC) device includes a delta-sigma modulator having at least one integrator and a quantizer configured to receive an output of the at least one integrator. The delta-sigma modulator also includes digital-to-analog converter (DAC) capacitor bank, a sampling capacitor bank, and a pre-charge capacitor bank, each selectively coupled to an input node of the at least one integrator. The delta-sigma modulator also includes a pre-charge signal generator coupled to the pre-charge capacitor bank. The pre-charge signal generator is configured to generate a pre-charge signal to charge the pre-charge capacitor bank based at least in part on an output code of the quantizer.

Delta-sigma converter with pre-charging based on quantizer output code

A weight management mat for passively and automatically monitoring weight for one or more individuals in a household. The weight management mat generally includes a housing having an upper mat and a lower mat between which is sealed a pair of perpendicular sensor arrays. Each sensor array includes fiber optic cables laid out in a grid pattern. One or more microbend inducers act to induce detectable microbends in the fiber optic cables when an individual steps on the upper mat. The change in light intensity caused by these microbends is recorded by photodetectors and processed by a microcontroller. The present invention may be utilized to identify each unique individual stepping on the present invention by the pressure map of their feet. Thus, recorded weight measurements may be tracked to aid in weight management.

Fiber-optic weight management mat with microbend inducers

An exemplary circuit includes a tracking circuit, a current estimator, a switch control logic, and a switching load circuit. The tracking circuit tracks a digital output signal of a delta-sigma modulator (DSM) and provides a tracking signal representing an average of the digital output signal during a time period. The current estimator determines an amount of loading to be applied to positive and negative reference voltages based on the tracking signal. The switching load circuit is coupled to positive and negative reference voltages of the DSM, the switching load circuit connects a selected amount of loading to the positive and negative reference voltages in response to a control signal to balance a reference load current applied to the DSM. The switch control logic provides the control signal to the switching load circuit based on the determined amount of loading to be applied to the positive and negative reference voltages.

Delta sigma ADC with output tracking for linearity

A dual delta-sigma modulator includes a first modulator, a second modulator, and a shared amplifier coupled to the first and second modulators. The first modulator includes an integrator configured to generate a first modulator output signal. The second modulator includes a second integrator configured to generate a second modulator output signal. The shared amplifier is configured to assist the first integrator integrating a difference between a first analog input signal and a first modulator output signal from the first modulator during a first period of time and to assist the second integrator integrate a difference between a second analog input signal and a second modulator output signal from the second modulator during a second period of time.

Amplifier sharing technique for power reduction in analog-to-digital converter

An operational amplifier includes an output stage, an input stage, a first auxiliary amplifier, and a second auxiliary amplifier. The output stage includes a first output transistor and a second output transistor. The input stage is configured to drive the output stage. The first auxiliary amplifier is coupled to an output of the input stage and to an input of the first output transistor. The first auxiliary amplifier is configured to bias the first output transistor for class AB operation and to isolate the input stage from a bias voltage applied to the first output transistor. The second auxiliary amplifier is coupled to the output of the input stage and to an input of the second output transistor. The second auxiliary amplifier is configured to bias the second output transistor for class AB operation, and to isolate the input stage from a bias voltage applied to the second output transistor.

Operational amplifier with class AB output

A delta-sigma Analog-to-Digital Converter (ADC) (IC) which includes an input feed-forward path extending from an input to the ADC to a feed-forward summing circuit disposed between a loop filter and quantizer of the ADC, and a filter disposed in the feed-forward path as an apparatus for improving distortion performance in the delta-sigma ADC. The filter may be a low pass filter, for example, a Resistor-Capacitor (RC) circuit. The filter may have a cut-off frequency outside the ADC's passband. The filtering provided may be continuous-time filtering, even if the delta-sigma ADC is a discrete-time delta-sigma ADC.

Delta-sigma analog-to-digital converter topology with improved distortion performance

Fiber optic weight management mat

A method for converting an analog signal to a digital signal is provided. Initially, a digital representation of a portion of an analog signal is generated. Residue of the analog signal is then sampled at a sampling instant so as to generate a residue sample. A signal having a frequency that is proportional to the voltage of the residue sample is generated, and the signal is measured to generate coarse and fine measurements of the frequency. A digital representation of the residue sample from the coarse and fine measurements is then generated.

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Frisco, TX, United States of America

Amit Kumar Gupta