Stmicroelectronics International N.v.

Stmicroelectronics Pvt. Ltd.

Stmicroelectronics S.r.l.

Synopsys, Inc.

Amit Katyal

Nitin Bansal

Massimiliano Picca

Joshipura Jwalant

Rupesh Khare

A magnitude difference between intrinsic positive and negative current components forming a PLL's charge pump output current is determined by simultaneously outputting the intrinsic positive and negative pump current components, and incrementally increasing a bias current added to one of the intrinsic current components (e.g., such that the total positive current component is gradually increased). Calibration control voltages generated by the calibration pump output current are measured to determine when magnitudes of the adjusted (e.g., positive) current component and the non-adjusted/intrinsic (e.g., negative) current component are equal, and the bias current amount required to achieve equalization is stored as a digital converter code. During subsequent normal PLL operations, the digital converter code is utilized to control the charge pump such that the magnitude of the positive current component is adjusted by the bias current amount such that the positive and negative current components are matched.

Phase locked loop circuit with charge pump up-down current mismatch adjustment and static phase error reduction

A phase locked loop includes a voltage-controlled oscillator and a current mirror circuit that supplies a drive current to the voltage-controlled oscillator. The current mirror circuit includes a filter between a bias current generator and current mirror transistor. The filter includes a first and a second switch driven in unison with a small duty cycle.

High frequency low-gain noise ring-type VCO oscillator leading to a low-noise/area PLL

An electronic circuit is described in which a charge pump-based digital phase locked loop circuit is augmented with additional circuitry to monitor and control noise and power consumption. The additional circuitry includes a comparator and a measurement stage configured to measure and adjust a unity gain bandwidth of the phase locked loop. In one embodiment, the measurement stage includes two frequency-to-current converters and associated current mirrors.

Phase locked loop circuit equipped with unity gain bandwidth adjustment

An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size portion of said device is coupled to said I/O rails for distributing portions of said device on the periphery of said chip. The device is coupled as small size portion on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.

Area-efficient distributed device structure for integrated voltage regulators

A phase lock loop (PLL) circuit incorporates switched capacitive circuitry and feedback circuitry to reduce the time to achieve a lock condition. During a first mode, the frequency of a voltage controlled oscillator (VCO) is used to adjust the control voltage of the VCO to achieve a coarse lock condition. During a second mode, a reference frequency is used to control a charge pump to more precisely adjust the control voltage to achieve fine lock of the PLL. Because the VCO frequency is significantly higher than the reference frequency, the control voltage is varied at a greater rate during the first mode. In some embodiments, the time to achieve lock may be further reduced by initializing the VCO control voltage to a particular voltage so as to reduce the difference between the control voltage at start-up and the control voltage at the beginning of the first mode during coarse lock.

Fast lock acquisition and detection circuit for phase-locked loops

An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip. The device is coupled as small size replica on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.

An area efficient distributed device for integrated voltage regulators comprising at least one filler cell connected between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip. The device is connected as small size replica on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.

A linear regulator with an N-type pass transistor includes an over-current protection circuit. A current sink is used as an indicator for an over-current condition and is coupled to the output of the linear regulator. The indicator is coupled to a feedback logic circuit that controls the current through the output load. The over-current protection circuit extensively uses N-type devices for various components including the output driver stage in the circuit. This results in reduced area for the over-current protection circuit.

Growing community of inventors

Ghaziabad, India

Amit Katyal