Synopsys, Inc.

Amit Gopal M Purohit

Denis Martin

Paras Chhabra

Anubhav Sinha

Salvatore Talluto

Ramalingam Kolisetti

Sorin Ioan Popa

Sai Manish Rao Marru

Sahil Soni

A first scan pattern may be received to test a first circuit block in an integrated circuit (IC) design and a second scan pattern may be received to test a second circuit block in the IC design. A first length of the first scan pattern may be different from a second length of the second scan pattern. The first scan pattern, the second scan pattern, or both the first scan pattern and the second scan pattern may be modified to make lengths of the first scan pattern and the second scan pattern equal.

Modifying scan patterns to enable broadcasting a scan enable signal to multiple circuit blocks

A method includes identifying state holding pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design, splitting each pattern of a plurality of patterns into a first part and a second part, reformatting the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns. The length of the first part is a function of a number of the identified pipeline stages.

Reformatting scan patterns in presence of hold type pipelines

Techniques for testing an integrated circuit (IC) are disclosed. A controller in the IC retrieves first testing data from a first memory in the IC. The controller transmits the first testing data to a first built-in self-test (BIST) core. The controller receives a response from the first BIST core, relating to a test at the first BIST core using the first testing data. The controller determines a status of the test relating to the IC based on the response.

Packetized power-on-self-test controller for built-in self-test

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Bengaluru, India

Amit Gopal M Purohit