Level One Communications, Inc.

Akros Silicon, Inc.

Amit Gattani

Jun Cai

John R Camagna

Paulius Mosinskis

Philip John Crawley

Paul James Hurst

David William Cline

Hiroshi Takatori

Stanley K Ling

A network device comprises an interface coupling an electronic device to a differential pair of signal lines, and an integrated active common mode suppression and electrostatic discharge protection circuit coupled to the interface in parallel to differential signal lines of the electronic device. First and second resistors are respectively coupled to the differential lines between the integrated active common mode suppression and electrostatic discharge protection circuit and the electronic device.

Electrostatic discharge protection circuit

A network device comprises an interface coupling an electronic device to a differential pair of signal lines, and an integrated active common mode suppression and electrostatic discharge protection circuit coupled to the interface in parallel to differential signal lines of the electronic device.

Embodiments disclosed herein describe a network device including a class AB common mode suppression (CMS) circuit coupled in parallel between a line voltage source and a physical layer (PHY) device that provides active EMI suppression and Phy device termination. A network connector is coupled to provide the line voltage source to the class AB CMS circuit. The class AB CMS circuit provides current to the PHY device, terminates open-drain transmit drivers of the PHY device and suppresses common mode noise thereby minimizing electromagnetic interference. In other embodiments, the class AB CMS circuit is coupled in parallel between the network connector and a physical layer (PHY) device. The class AB CMS circuit suppresses common mode noise, and terminates open-drain transmit drivers of the PHY device, thereby minimizing electromagnetic interference.

Network devices with solid state transformer and class AB output stage for active EMI suppression and termination of open-drain transmit drivers of a physical device

A method and apparatus for providing a self-sustaining precise voltage and current feedback biasing loop. The present invention provides a circuit for initially biasing the bandgap and master bias current generator at startup. The feedback biasing loop has loop dynamics that are chosen such that the gain of the positive feedback loop is less than one so that the loop will not oscillate under normal operation after power-up.

Method and apparatus for providing a self-sustaining precision voltage and current feedback biasing loop

A system and method for regulating the duty cycle of a digital clock signal derived from an oscillator signal. The oscillator signal is DC-biased to a DC value representing an average DC value of an ideal digital clock signal having a 50% duty cycle. The DC-biased oscillator signal is compared to a reference voltage. The digital clock signal is generated as a substantially square wave signal having first and second logic levels, and is generated in response to the comparison of the DC-biased oscillator signal and the reference voltage. The DC component of the generated digital clock signal is then used as the reference voltage.

Self-referencing slicer method and apparatus for high-accuracy clock duty cycle generation

A method and apparatus for matching common mode output voltage at a switched-capacitor to continuous-time interface. An active continuous time summation circuit is used at the output of the switched-capacitor stage to derive the common mode level that is at the output of the switched-capacitor stage. This derived signal is filtered to remove any noise component remaining in it, and is then used as the reference common mode signal in the continuous time stage. This forces the output common mode, and hence the input common mode of the unity gain amplifier stage, to track the common mode output of the switched-capacitor stage. This adaptive tracking eliminates the common mode interface error, which could be present and could vary from die to die (due to parasitic variations). This technique ensures proper tracking of the DC levels between the negative and the positive terminals of the unity gain amplifier, which is essential for low distortion operation of the amplifier.

Method and apparatus for matching common mode output voltage at a switched-capacitor to continuous-time interface

A timing recovery circuit is disclosed that prevents phase error over-compensation. The timing recovery circuit includes a phase scanner for determining when phase error over-compensation has occurred and generating a signal for preventing dual phase compensation in response thereto thereby providing an accurate recovered clock signal. The timing recovery circuit also includes a feed-forward equalizer having a plurality of taps providing coefficients for filtering and adapting the input timing recovery circuit to an input signal. The phase scanner compares the tap coefficients to generate signal for preventing phase over-compensation by the feed-forward equalizer. A phase detector is provided for sampling coefficients from the feed-forward equalizer, error signals and output data and generating a phase signal used to generating the recovered clock signal. The signal for preventing phase over-compensation is mixed with the phase signal to generate the recovered clock signal.

Apparatus and method for performing timing recovery

A system and method for calibrating a multi-bit feedback quantizer in a delta-sigma modulation system. A digital data pattern corresponding to a particular DAC code of a multi-bit digital-to-analog converter is transmitted in the transmit channel, where the DAC code is proportional to an analog voltage signal. An effective DC component of the digital data pattern is realized and converted to corresponding digital DC component values. A predetermined number of samples of the digital DC component values are averaged to provide an average sample value. A digital code in the multi-bit feedback quantizer is replaced with the average sample value.

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Roseville, CA, United States of America

Amit Gattani