Cadence Design Systems, Inc.

Amit Dua

Amit Kumar Sharma

Manu Chopra

Amit Aggarwal

Abhishek Raheja

Vincent Gregory Reynolds

Hemant Gupta

The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include receiving an electronic design at a verification environment. Embodiments may also include performing a simulation of a portion of the electronic design in an X-propagation mode. Embodiments may further include determining whether the simulation is entering an element during a time range and determining whether a clock/reset associated with the element has an active X-edge. If the clock/reset has an active X-edge, embodiments may include preventing a recordation of coverage metrics during the time range.

System, method, and computer program product for analyzing X-propagation simulations

Methods for debugging a failure in a logic circuit design simulation by tracing a X-value are provided. In one aspect, a method includes detecting during a X-propagation logic circuit design simulation a failure at a register transfer level of a logic circuit comprising one or more logic blocks and tracing a X-value in a data path of the one or more logic blocks until the X-value is observed in a control path of the one or more logic blocks. The method also includes identifying a logic block comprising a control signal of the control path in which the X-value is observed, and identifying the logic block in which the X-value is observed as a root cause of the failure. Systems and machine-readable media are also provided.

Debugging failures in X-propagation logic circuit simulation

Growing community of inventors

Fremont, CA, United States of America

Amit Dua