Cadence Design Systems, Inc.

Amit Dhuria

Naresh Kumar

Krishna Prasad Belkhale

Prashant Sethia

Pawan Kulshreshtha

Pradeep Yadav

Vibhor Garg

Saulius Kersulis

Igor Keller

Sharad Mehrotra

Arvind Nembili Veeravalli

Umesh Gupta

Manuj Verma

Jeannette Sutherland

Sarath Jayalath Kirihennedige

Shashank Tripathi

Sri Harsha Pothukuchi

Edward J Martinage

Jean Pierre Hiol

Sri Harsha Venkata Pothukuchi

Embodiments included herein are directed towards a method for comparing constraint sets. The embodiments may include determining, using at least one processor, at least one arrival propagation time corresponding to at least one endpoint, the at least one endpoint associated with a first constraint set and a second constraint set. The embodiments may further include creating, using the at least one processor, a first tag associated with the first constraint set and a second tag associated with the second constraint set. The embodiments may also include determining, using the at least one processor, at least one of: a non-equivalent path exception corresponding to the at least one endpoint and based at least in part on at least one of the arrival propagation time, the first tag, and the second tag; and an equivalent path exception corresponding to the at least one endpoint.

System and method for comparing circuit design constraint sets

An approach is described for a method, system, and product for deferred merge based method for graph based analysis to reduce pessimism. According to some embodiments, the approach includes receiving design data, static and/or statistical timing analysis data, identifying cells and interconnects for performing graph based worst case timing analysis where merger of signals is deferred based on one or more conditions to reduce pessimism, and generating results thereof. Other additional objects, features, and advantages of the invention are described in the detailed description, figures, and claims.

Method, system, and product for deferred merge based method for graph based analysis pessimism reduction

An approach is described for a method, system, and product, that includes identification/generation of a synthesized netlist for use in optimization and placement, generation and utilization of multiple uncertainty values for an early clock tree for guiding optimization and placed of circuit elements in a placeopt process that operates on a path by path basis. In some embodiments, the approach further comprises execution of clock tree synthesis, and routing the synthesized clock tree. In some embodiments, uncertainty values are propagated along data paths where each data path is associated with an uncertainty value, and where each path is optimized and placed on a path my path basis in order to meeting timing requirements and one or more design goals.

Method, system, and product for an improved approach to placement and optimization in a physical design flow

The present embodiments relate to static timing analysis (STA) of circuits. The STA can be carried out concurrently for multiple-mode-multiple-corners (MMMC) for circuits including combinational loops. The STA includes determining hard breaking points in the loop associated with each single-mode-single-corner (SMSC) view. The STA also includes merging constraints of all SMSC views to generate a merged set of constraints. The STA includes running MMMC STA for the circuit based on the merged set of constraints. The STA also includes determining a soft breaking point for the loop in the MMMC view for timing propagation and settling. The STA maintains consistency of breaking points across SMSC and MMMC views.

Deterministic loop breaking in multi-mode multi-corner static timing analysis of integrated circuits

According to certain aspects, the present embodiments include techniques for performing a single timing analysis run for a plurality of views representing different modes and/or corners. An embodiment analyzes and maintains relevant timing information that is different for different views, but otherwise maintains the same information for all views. This allows each individual view in a single run to be analyzed in the same manner as separate runs for each separate view, thereby ensuring the same QoR. These and other embodiments provide substantial savings in runtime and memory consumption over other approaches.

Shared timing graph propagation for multi-mode multi-corner static timing analysis

Electronic design automation systems, methods, and media are presented for hierarchical timing analysis with multi-instance blocks. Some embodiments involve generation of a combined timing context for instances of a multi-instance block. Such embodiments may merge timing context information with multi-mode multi-context (MMMC) views for different instances of a multi-instance block. Other embodiments involve efficient merging of instance timing contexts during block level static timing analysis. Various different embodiments involve separate or hybrid merged timing analysis based on a user selection.

Timing context generation with multi-instance blocks for hierarchical analysis

Disclosed are techniques for multi-mode, multi-corner physical optimization of electronic designs. These techniques identify an electronic design and a global set of views. Timing information is characterized with the global set of views for the electronic design. A set of active views is generated at least by pruning one or more views from the global set of views for a first node in the electronic design while maintaining the one or more views for a second node in the set of active views. The electronic design is then associated with the set of active views that is stored in a data structure in a non-transitory computer accessible storage medium.

Methods, systems, and articles of manufacture for multi-mode, multi-corner physical optimization of electronic designs

Electronic design automation systems, methods, and media are presented for hierarchical timing analysis with multi-instance blocks. Some embodiments involve generation of a combined timing context for all instances of a multi-instance block. Such embodiments may merge timing context information with multi-mode multi-context (MMMC) views for different instances of a multi-instance block. Other embodiments involve efficient merging of instance timing contexts during block level static timing analysis. Various different embodiments involve separate or hybrid merged timing analysis based on a user selection.

Hierarchical timing analysis for multi-instance blocks

The present disclosure relates to a computer-implemented method for use with an electronic design. Embodiments include identifying, using one or more processors, a plurality of sibling nets associated with the electronic design and determining if the plurality of sibling nets have a same input slew rate. If the plurality of sibling nets do not have a same input slew rate, embodiments also include determining a delay calculation (DC) for each of the plurality of sibling nets. If the plurality of sibling nets do have a same input slew rate, embodiments further include sharing a stored DC with the plurality of sibling nets.

System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design

A static timing analysis method for input/output modes of an integrated circuit design, that includes loading the integrated circuit design described in a hardware description language into a memory. An active zone for static timing analysis is defined, which comprises logic and interconnect between an input/output port and a selected level of sequential logic elements upstream from an input port and downstream from an output port. A description of the active zone is generated using the hardware description language. Then a static timing analysis is performed on the logic of the active zone.

High performance static timing analysis system and method for input/output interfaces

A system and method are provided for generating a structurally-aware timing model for operation of a predetermined circuit design. The timing model is generated to have a plurality of timing arcs representing timing characteristics of the circuit design. Additionally, terminal pairs of the circuit design are evaluated to determine characteristic structural weights for selected paths through the circuit design. The structurally-aware timing model may then be incorporated into a top-level hierarchical circuit design for timing analyses and pessimism removal to arrive at realistic timing characteristics. The structural weights are particularly helpful in an AOCV-type pessimism removal post-process.

System and method for generating and using a structurally aware timing model for representative operation of a circuit design

A system and method are provided for pessimism reduction of a timing database provided for optimization of a circuit design. Pessimism is reduced through generation of a hybrid graph-based static timing analysis (GBA) and path-based static timing analysis (PBA STA) database. PBA is selectively performed on the most critical GBA identified timing violations with the goal of reducing erroneous pessimism in operational timing characteristics passed on to the physical implementation corrective optimizer module to thereby reduce unnecessary fixing and transformations upon the circuit design to correspondingly reduce design time, temporary storage space, needed processing power for timing closure and to result in a finished operable and tangible circuit device with reduced area, power requirements, and decreased cost.

System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit design

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Cupertino, CA, United States of America

Amit Dhuria