Xilinx, Inc.

Pwc Product Sales LLC

Amit Dhir

Krishna Rangasayee

Vasudeva Sankaranarayanan

Tarun Sharma

Vasundhara Rungta

Surya Turlapati

Prachi Agrawal

Pradnesh Deshmukh

Mathew George

Francis G Melinn

Henry Huang

Pranati Dang

Michael Reid

Systems, methods, and graphical user interfaces (GUIs) for ingesting and enriching data regarding a plurality of entities are provided. A first data set comprising company data and a second data set comprising customer data are ingested. The first data set is processed to generate a processed data set. The first data set may be processed by applying an entity matching technique, wherein one or more data elements are generated based on whether an entity of the first data set and an entity of the second data set are commonly associated. The first data set may additionally or alternatively be processed by applying a statistical matching technique, wherein one or more predicted data elements are generated based on similarity between an entity of the first data set and one or more entities of the second data set.

Automated data set enrichment, analysis, and visualization

According to various embodiments of the present invention, an intelligent framer/mapper integrates the framer, mapper, and the controlling function of the host processor, implemented as either a soft processor or an embedded processor, into a single device, such as a programmable logic device. The use of the soft processor or embedded processors on the device reduces the load on the host processor on the line card. According to some aspects of the invention, the devices takes advantage of an embedded, dedicated processor and/or soft processor(s) to allow for a distributed processing on a single chip.

Integrated circuit and method of employing a processor in an integrated circuit

Method and apparatus for a wireless local area network programmable logic device is described. More particularly, a field programmable gate array (FPGA) is coupled to memory having programming instructions for configuring the FPGA with a medium access layer selected from more than one type of medium access layers. A physical layer is hardwired or embedded on the FPGA, or a separate integrated circuit for the physical layer is used. Additionally, the memory comprises programming instructions for a baseband controller, and may include programming instructions for a baseband processor, for configuring the FPGA in accordance therewith. In this manner, a single physical layer may be used with an FPGA to provide a multi-platform application specific standard product (ASSP). This is especially advantageous for providing multi-platform devices for use in countries or applications where one or more standards may be employed.

Programmable logic device for wireless local area network

The present invention is a programmable integrated circuit that can be used to handle different communication specifications. In one embodiment, the integrated circuit contains at least two physical layer modules, a media independent interface and a media access control module. The physical layer modules are preferably fixed logic components embedded in programmable logic fabric. In another embodiment, the integrated circuit contains a physical layer module and at least two media access control modules. The physical layer module is preferably a fixed logic component embedded in programmable logic fabric.

Configurable communication integrated circuit

Growing community of inventors

San Jose, CA, United States of America

Amit Dhir