Stmicroelectronics International N.v.

Stmicroelectronics S.r.l.

Stmicroelectronics S.a.

Amit Chhabra

Vikas Rana

Abhishek Jain

Harsh Rawat

Tanmoy Roy

Nitin Jain

Swapnil Bahl

Kailash Digari

Andrea Mario Veggetti

Christophe Lecocq

Dibya Dipti

Kaya Can Akyel

Jatin Fultaria

When powering-up or exiting from a sleep mode, the ramping up of various supply voltage nodes may occur at different rates. Thus, in a dual-rail memory circuit, a first voltage rail may be at voltage before a second voltage rail. Such a transient state of operation may lead to current spikes that unnecessarily draw power and introduce undesired inefficiency. An internal sleep signal generation circuit in the dual-rail memory circuit precisely controls an internal sleep signal such that the transition from off or sleep mode to operating mode is set to assure that the supply voltage nodes are close enough to the at-voltage operating level before releasing the sleep mode.

System and method for automatic detection of power up for a dual-rail circuit

An integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A body bias voltage generator generates a positive body bias voltage, and a negative body bias voltage in the ground body bias voltage. A multiplexer selectively outputs one of the positive, negative, or ground body bias voltage to the doped well region of the semiconductor substrate based on the temperature of the semiconductor substrate.

Body bias multiplexer for stress-free transmission of positive and negative supplies

An integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A threshold detector selectively applies either a first voltage or second voltage to the doped well region based on whether the temperature of the semiconductor substrate is above or below a threshold temperature.

Ultra-low voltage temperature threshold detector

According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.

System and method for improving memory performance and identifying weak bits

A multi-supply dual port register file is disclosed. The register file may be used for transferring data between two power domains that operate on different voltages or frequencies. The register file comprises a memory cell that stores the data transferred between the domains. The memory cell may be independently supplied by a reference voltage independent of that of the memory periphery. A write power domain write data to the memory cell in accordance with its operating voltage and frequency and an independent read power domain may read data from the memory cell in accordance with its independent operating voltage and frequency. The register file facilitates efficient crossing between the read and write power domains.

Multi-supply dual port register file

An SRAM cell is formed of FDSOI-type NMOS and PMOS transistors. A doped well extends under the NMOS and PMOS transistors and is separated therefrom by an insulating layer. A bias voltage is applied to the doped well. The applied bias voltage is adjusted according to a state of the memory cell. For example, a temperature of the memory cell is sensed and the bias voltage adjusted as a function of the sensed temperature. The adjustment in the bias voltage is configured so that threshold voltages of the NMOS and PMOS transistors are substantially equal to n and p target threshold voltages, respectively.

Method of minimizing the operating voltage of an SRAM cell

A dual-rail memory circuit having a sleep generation circuit configured to prevent undesired currents from being generated during power-up and while transitioning power states. When a dual-rail memory circuit is powering-up or exiting from a sleep mode, the ramping up of various supply voltage nodes may occur at different rates. Thus, in a dual-rail memory circuit, a first voltage rail may be at voltage before a second voltage rail. Such a transient state of operation may lead to current spikes that unnecessarily draw power and introduce undesired inefficiency. An internal sleep signal generation circuit in a dual-rail memory circuit may be used to precisely control an internal sleep signal such that the transition from off or sleep mode to operating mode is set to assure that the supply voltage nodes are close enough to the at-voltage operating level before releasing the sleep mode.

A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode.

Method and apparatus for testing of a memory with redundancy elements

A system for testing faults in shadow logic includes a sequential block coupled to a shadow logic block and a delaying block to receive test patterns for testing the shadow logic block. The delaying block delays the test patterns by an access time of the sequential block to generate delayed test patterns. The delayed test patterns are passed to the shadow logic block for testing faults.

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Delhi, India

Amit Chhabra