Micron Technology Incorporated

Amit Bhardwaj

Naveen Bolisetty

Suman Kumari

A command to migrate data from a source address to a destination address is detected. One or more parameters associated with the source address are provided as input to a trained machine learning model. A read verify relevance if received as output from the trained machine learning model. Responsive to determining that the read verify relevance satisfies a condition, the command is performed to migrate the data.

Machine learning assisted read verify in a memory sub-system

A write request is determined to comprise at least a partial translation unit. A size of the partial translation unit is smaller than a size of a predefined translation unit. A first entry in a translation map is identified. The translation map maps a plurality of translation units to a plurality of physical blocks. The first entry identifies a first physical block corresponding to the predefined translation unit. A second entry in the translation map is created. The second entry identifies a second physical block. An association between the first entry and the second entry is created, such that the second entry corresponds to the predefined translation unit. A write operation is performed to write a set of data corresponding to the partial translation unit to the second physical block.

Write request with partial translation unit mapped to entries that are linked using a pointer

Disclosed is a system including a memory device having a plurality of physical memory blocks and associated with a logical address space that comprises a plurality of zones, wherein each zone comprises a plurality of logical block addresses (LBAs), and a processing device, operatively coupled with the memory device, to perform operations of receiving a request to store data referenced by an LBA associated with a first zone of the plurality of zones, obtaining a version identifier of the first zone, obtaining erase values for a plurality of available physical memory blocks of the memory device, selecting, in view of the version identifier of the first zone and the erase values, a first physical memory block of the plurality of available physical memory blocks, mapping a next available LBA within the first zone to the first physical memory block, and storing the data in the first physical memory block.

Zone-aware memory management in memory sub-systems

Disclosed is a system that comprises a memory device comprising a plurality of memory planes and a processing device, operatively coupled with the plurality of memory planes, to perform operations that include, identifying a first block residing on a memory plane of the memory device, wherein the first block is associated with an error condition; and responsive to identifying the first block, performing an error recovery operation to replace the first block with a second block, wherein the second block resides on the memory plane.

Remapping bad blocks in a memory sub-system

A write command directed to a target zone of a memory device is received. Responsive to determining that a first portion of the target zone is open, the write command is executed at the first portion. Responsive to determining that the first portion has reached a threshold capacity, a second portion allocated to a media management pool is identified. The second portion satisfies a threshold capacity. One or more blocks associated with the second portion are erased. The second portion is allocated to a free block list.

Block allocation and erase techniques for sequentially-written memory devices

An error associated with host data written to a page of a storage area of a memory sub-system is detected. A determination is made that parity data corresponding to the host data is stored in a cache memory of the memory sub-system. A data recovery operation is performed based on the parity data stored in the cache memory.

Data recovery based on parity data in a memory sub-system

An on-chip copy command is detected. The on-chip copy command comprises a source address referencing a plane of a memory device, and a destination address referencing the plane. A read verify relevance is estimated by processing, by a machine learning mode, one or more parameters associated with data stored at the source address. Responsive to determining that the read verify relevance satisfies a threshold condition, the on-chip copy command is performed.

Host data is written to a set of pages of a page stripe of a storage area of a memory sub-system. A set of exclusive or (XOR) parity values corresponding to the host data written to a portion of the set of pages of the storage area is generated. An additional XOR parity value is generated by executing an XOR operation using the set of XOR parity values. Parity data including the set of XOR parity values and the additional XOR parity value is stored in a cache memory of the memory sub-system. The parity data is written to an available page stripe of the storage area.

Management of parity data in a memory sub-system

A number of data access operations is tracked where the data access operations are associated with each of a plurality of portions of a translation map. The translation map maps a plurality of logical block addresses to a plurality of physical block addresses of the memory device. A criterion to perform a garbage collection operation is determined to be satisfied. The garbage collection operation is to be performed on a block of the memory component. The block for performing the garbage collection operation is identified based on the number of data access operations associated with each of the plurality of portions of the translation map. The garbage collection operation is performed on the identified block.

Media management based on data access metrics

Disclosed is a system that comprises a memory device comprising a plurality of memory planes and a processing device, operatively coupled with the memory device, to perform operations that include, generating a block stripe of the memory device, wherein the block stripe comprises a plurality of blocks arranged across the plurality of memory planes; determining that a first block of the plurality of blocks of the block stripe is associated with an error condition, wherein the first block is associated with a first plane of the plurality of planes; and responsive to determining that the first block of the plurality of blocks of the block stripe is associated with the error condition, performing an error recovery operation on the plurality of blocks to replace the first block with a replacement block in the block stripe.

A plurality of zone reset counters and a global reset counter are maintained. A zone reset counter represents a number of times a respective zone of a memory device has been reset. The global reset counter represents a measure of central tendency of the plurality of zone reset counters. A write command directed to a target zone of the memory device is received, and responsive to determining that a target portion of the target zone is not open, a value of the zone reset counter of het target zone is compared to the value of the global reset counter. If the value of the target zone reset counter equals or exceeds the value of the global reset counter, a portion from a free block list is allocated to the target zone. The allocated portion has a highest program erase count among the one or more portions in free block list.

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Hyderabad Telangana, India

Amit Bhardwaj