Marvell International Limited

Marvell Israel (misl) Ltd.

Marvellworld Trade Ltd.

Amit Avivi

Aron Wohlgemuth

Tsahi Daniel

Nafea Bishara

Yuval Cohen

Yosef Solt

Youval Nachum

Dimitry Melts

Ehud Sivan

Amir Gabai

Michael Moshe

Roman Kleinerman

Systems and methods are provided for customer premises equipment (CPE) on a passive optical network (PON). A system includes a packet processor having at least an active mode and a sleep mode, the packet processor configured to processes streams of data packets received in a data plane from an optical line terminal (OLT) through the PON when in an active mode and to enter the sleep mode when not receiving data packets in the data plane. A system further includes a micro-controller, separate from the packet processor, configured to receive from an OLT operation and management (OAM) messages that are transmitted in a control plane, and to process the OAM messages by, selectively transmitting to a central office, without waking up the packet processor, an acknowledgement message, or waking up the packet processor to receive data packets in the data plane.

Systems and methods for advanced power management for optical network terminal systems on chip

An apparatus having a corresponding method comprises a transmit circuit to transmit data, the transmit circuit comprising a transmit input circuit to input the data, and an address for the data, to the transmit circuit, an encoder to encode the data according to the address for the data, comprising an encode select circuit to select one of a plurality of keys based on the address for the data, and an encoding circuit to encode the data using the key selected by the encode select circuit, and a transmit output circuit to output the encoded data.

System and method for encoding data transmitted on a bus

A network switch including a plurality of stack units sequentially linked to each other. Each stack unit includes a port, a forwarding engine, a first interface, and a second interface. The second interface of each stack unit is linked to the first interface of a subsequent stack unit. The second interface of a last stack unit is linked to the first interface of a first stack unit. In response to a packet traveling in a first direction from the first stack unit to the last stack unit and a link between a second stack unit and a third stack unit being inoperative, the forwarding engine of the second stack unit returns the packet in a second direction to a preceding stack unit. The packet travels in the second direction from the preceding stack unit to the first stack unit, to the last stack unit, and to the third stack unit.

System and method for handling packets in a stackable network switch

A network switch including first, second, and third stack units. The first stack unit includes a first interface configured to communicate, via a first link, with a second stack unit of the network switch; a second interface configured to communicate, via a second link, with a third stack unit of the network switch; and a forwarding engine configured to transfer a first packet to the first interface, and in response to the first link being inoperative, to (i) receive the first packet from the first interface, and (ii) transfer the first packet received from the first interface to the second interface.

Fast failover recovery for stackable network switches

An embodiment of a network device includes a plurality of switch cores and a plurality of ports for receiving and transmitting data frames on a network disposed on a single integrated circuit, where switch core is coupled to a subset of the plurality of ports. The network device includes a deactivator configured to selectively deactivate at least a portion of one or more switch cores among the plurality of switch cores on the single integrated circuit, and the network device is configured to forward data frames among the plurality of ports based on a configuration of active portions of the plurality of switch cores. The deactivated portions may include ingress processing pipelines, egress processing pipelines, and/or entire switch cores. The portions of the switch cores to be deactivated may be dynamically be determined based on connectors of the integrated circuit.

Multiple core network device with core redundancy

A network switch including a plurality of stack units and a plurality of links. Each of the stack units includes a port, a plurality of interfaces, and a forwarding engine in communication with the interfaces and the port. Each of the plurality of links connects one of the interfaces of one of the stack units to another one of the interfaces of another one of the stack units. When one of the links is down, a loop flag in a first packet to be transferred by a corresponding one of the interfaces of a corresponding one of the stack units over the one of the links is toggled; and the forwarding engine of the corresponding one of the stack units is configured to transfer the first packet to another one of the interfaces of the corresponding one of the stack units for transfer over a different one of the links.

An apparatus includes a network port and a switch management processor. The network port receives packets over a network, where the packets include a management packet and a trigger packet. The switch management processor executes a command in selected management packets received over the network when a trigger pattern generated based on the trigger packet matches a bit pattern stored in memory. The bit pattern is stored in the memory during a predetermined period after the management packet is received. The predetermined period is selected based on a desired security level.

Remote network device management

A data processing system includes a memory configured to store data in a plurality of addressable storage spaces thereof, wherein the memory includes a first data port and a second data port, a first functional block configured to access the memory via the first data port to perform a logic operation, and a second functional block configured to access the memory via the second data port to perform soft error scrubbing in the data stored in the memory.

System and method for soft error scrubbing

A stack unit for a stackable network switch, the stack unit having corresponding methods and computer programs, comprises a network port to exchange packets with a network; two stacking interfaces each to exchange the packets over a respective stacking link with another stack unit, wherein each stacking interface is assigned to the other stacking interface as an alternate stacking interface; and a forwarding engine to transfer the packets among the stacking interfaces and network port; wherein when one of the stacking links is down, the respective stacking interface toggles a loop flag in each packet received from the forwarding engine, and returns each received packet to the forwarding engine; and wherein the forwarding engine transfers each packet received from one of the stacking interfaces to the respective alternate stacking interface when the loop flag for the packet is set.

An apparatus having a corresponding method comprises a memory; a plurality of ports comprising one or more network ports to send and receive data packets and to receive management packets, wherein each of the management packets comprises one or more commands, and wherein the commands comprise one or more of the group consisting of a command to read data from the memory, and a command to write data to the memory, and a central processing unit (CPU) port to transmit packets addressed to a CPU; a forwarding engine to transfer the data packets between the ports according to a forwarding table stored in the memory; a protocol unit to identify the management packets; and a management unit to execute the commands; wherein the management packets bypass the CPU port.

A circuit having a corresponding method comprises one or more circuits each to produce one or more status signals, wherein each of the status signals represents a status of a respective one of the one or more circuits; a memory; a memory controller to store a plurality of samples of the one or more status signals in the memory; a plurality of input/output terminals; an interface in communication with one or more of the input/output terminals; and a debug circuit to transfer the one or more samples of the status signals from the memory to the interface.

Growing community of inventors

Tel-Mond, Israel

Amit Avivi