Intel Corporation

Qualcomm Incorporated

Amit Aneja

Anatoly Gelman

Bruno Achauer

Maciej Adam Kaminski

Jorge Serratos Hernandez

Rahul Gulati

Dhawal Srivastava

Olivier Alavoine

Amod Phadke

Sina Dena

Michael Tipton

Vanamali Bhat

Michael James Smith

Mithali Shivkumar

Sriram Hariharan

Robert Mahieu

James Cheng-Huan Wu

Prachin Sheshrao Bhoyar

Takeshi Kevin Yamane Musgrave

Mingcheng Zhu

Felipe Regis Goncalves Cabral

Wei-Yu Tsai

Jayaram Puttaswamy

A method for a clock monitoring subsystem of a system-on-chip (SoC) supporting dynamic clock scaling and voltage gating is described. The method includes generating a set of clocks. The method also includes routing a selected one of the set of clocks for frequency measurement through one or more clock routing subsystems. The method further includes adjusting a frequency of the selected clock after the selected clock is routed through the clock routing subsystems. The method also includes communicating a sideband signal to indicate the adjusted frequency of the selected clock.

Clock monitoring subsystem for supporting dynamic frequency scaling and clock gating

Aspects of the disclosure are directed to voltage sensing for safety-critical applications. In accordance with one aspect, the disclosure includes a multi-phase ring oscillator (RO) configured to operate in a first voltage domain; a frequency counter coupled to the multi-phase RO, the frequency counter configured to accumulate a plurality of phase cycles from the multi-phase RO over a time duration to generate a digital count word; an alarm processor coupled to the frequency counter, the alarm processor configured to receive an alarm state signal from the frequency counter; and a heartbeat detector coupled to the multi-phase RO, the heartbeat detector configured to operate in a second voltage domain and configured to detect a periodic recurrence of a heartbeat pulse to determine an integrity of the sensor function as a whole and alarm state signal in particular.

Voltage sensor with in-range check for safety-critical applications

This disclosure provides systems, methods, and devices for vehicles with automated driving systems. In a first aspect, a method of isolation in an automated driving system includes detecting the error in a first domain of the automated driving system, isolating a second domain of the automated driving system from the first domain, maintaining operation of the second domain after isolating the second domain from the first domain, and bypassing, by the second domain, the first domain to transmit notifications to an external controller via a first communication interface. Other aspects and features are also claimed and described.

Domain isolation in an automotive automated driving system

Aspects relate to monitoring timing margin of logic paths and its degradation through an integrated circuit. In one example an integrated circuit has a logic path formed in the integrated circuit. A monitor circuit is formed in the integrated circuit near the logic path and configured to monitor a condition of the logic path and to generate a diagnostic code sequence to indicate the condition of the logic path over time. A monitor controller is configured to receive diagnostic codes of the diagnostic code sequence, to determine a condition of the integrated circuit based on the diagnostic code sequence, and to initiate a remedial action in response to the condition of the integrated circuit.

Remedial action in an integrated circuit in response to a monitor circuit diagnostic code sequence

Input images are partitioned into non-overlapping segments perpendicular to a disparity dimension of the input images. Each segment includes a contiguous region of pixels spanning from a first edge to a second edge of the image, with the two edges parallel to the disparity dimension. In some aspects, contiguous input image segments are assigned in a 'round robin' manner to a set of sub-images. Each pair of input images generates a corresponding pair of sub-image sets. Semi-global matching processes are then performed on pairs of corresponding sub-images generated from each input image. The SGM processes may be run in parallel, reducing an elapsed time to generate respective disparity sub-maps. The disparity sub-maps are then combined to provide a single disparity map of equivalent size to the original two input images.

Parallelism in disparity map generation

Various systems and methods for implementing distributed object detection processing are described herein. An object detection system includes a plurality of computer vision accelerators to process a respective plurality of portions of an input image and produce a list of detected objects in the respective plurality of portions of the input image; and a processor subsystem to: combine the list of detected objects from each of the plurality of computer vision accelerators, to produce a combined list of detected objects; sort the combined list of detected objects; and remove duplicate entries in the combined list of detected objects to produce an output list of detected objects.

Distributed object detection processing

A system for managing memory resources related to boot, including a memory; a boot configuration circuit, configured to designate one or more memory regions as a first type or a second type, the first type requiring scrubbing before beginning system operation, and the second type permitting scrubbing after beginning system operation; one or more processors, configured to scrub the memory regions of the first type; define a first caching policy of one or more memory regions of the second type; and begin system operation before scrubbing memory regions of the second type.

Memory management

Technologies for an advanced driver assist system (ADAS) with adaptive memory pre-training include a computing device and a safety microcontroller in communication with a serial link and a general-purpose I/O (GPIO) link. Out of reset, the computing device determines whether a full memory training signal is raised via the GPIO link. If not raised, the computing device executes a fast boot path to initialize a memory controller with a pre-trained memory parameter data set and performs margin tests to check the validity of the pre-trained memory parameter data set. If the full memory training signal is raised, the computing device executes a slow boot path to generate the pre-trained memory parameter data set. The safety microcontroller may receive a message requesting full memory training via the serial link and, in response, hold the computing device in reset and raise the full memory training signal. Other embodiments are described and claimed.

Technologies for fast boot with adaptive memory pre-training

Growing community of inventors

Chandler, AZ, United States of America

Amit Aneja