Cadence Design Systems, Inc.

Freescale Semiconductor,inc.

Amit Aggarwal

Amit Kumar Sharma

Manu Chopra

Abhishek Raheja

Ashish Malhotra

Amit Dua

Ankit Pal

Vincent Gregory Reynolds

Hemant Gupta

Himanshu Goel

Andrey Evgenevich Malkov

Rohit Gupta

Evgeny A Shevchenko

The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include receiving an electronic design at a verification environment. Embodiments may also include performing a simulation of a portion of the electronic design in an X-propagation mode. Embodiments may further include determining whether the simulation is entering an element during a time range and determining whether a clock/reset associated with the element has an active X-edge. If the clock/reset has an active X-edge, embodiments may include preventing a recordation of coverage metrics during the time range.

System, method, and computer program product for analyzing X-propagation simulations

Methods for debugging a failure in a logic circuit design simulation by tracing a X-value are provided. In one aspect, a method includes detecting during a X-propagation logic circuit design simulation a failure at a register transfer level of a logic circuit comprising one or more logic blocks and tracing a X-value in a data path of the one or more logic blocks until the X-value is observed in a control path of the one or more logic blocks. The method also includes identifying a logic block comprising a control signal of the control path in which the X-value is observed, and identifying the logic block in which the X-value is observed as a root cause of the failure. Systems and machine-readable media are also provided.

Debugging failures in X-propagation logic circuit simulation

An integrated circuit (IC) includes a first I/O cell, a logic cell, a trigger signal generation circuit, and a second I/O cell having a voltage selection pin. I/O interfaces of the first I/O cell receive first and second supply voltages, respectively, and I/O interfaces of the second I/O cell receive third and fourth supply voltages, respectively. The first I/O cell generates a first trigger signal when the first supply voltage reaches a first predetermined voltage. The logic cell receives the first trigger signal and generates a safe-state signal. The trigger signal generation circuit generates a second trigger signal when the third supply voltage reaches a second predetermined voltage. The voltage selection pin receives the safe-state signal and the second trigger signal and sets the second I/O cell in a safe-state mode, which protects the second I/O cell from over voltage damage.

Integrated circuit with multi-voltage input/output (I/O) cells

An integrated circuit (IC) includes multiple circuit modules that have specific clocking requirements, multiple clock sources (e.g., PLLs, duty cycle re-shaper, etc.), and at least one clock input port. The clock sources have specific clock source specifications, and the circuit modules have specific clocking requirements. The clock sources are selected based on an identification of the most common clocking requirements, and then placed at routing distances measured from the input port that are less than corresponding predetermined maximum routing distances such that the clocking requirements of the circuit modules are met. The IC thus generates clock signals internally, rather than externally.

Clock distribution architecture for integrated circuit

The present disclosure relates to a computer-implemented method for electronic design verification. The method may include providing, using a processor, a low-power electronic design and determining if a power domain associated with the low-power electronic design is active. The method may further include identifying, at a register transfer level (RTL) at least one X value associated with an active power domain wherein identifying occurs during a simulation.

System, method, and computer program product for verification using X-propagation

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Ghaziabad, India

Amit Aggarwal