Intel Corporation

Amit A Merchant

Darrell D Boggs

David J Sager

Nitin V Sarangdhar

Dion Rodgers

Matthew A Fisch

Rajesh Kota

Rachel Hsu

Mickey L Fandrich

Michael W Rhodehamel

Neal R Mielke

James M Brayton

Keshavan K Tiruvallur

Peter D MacWilliams

Gregory E Atwood

Michael D Upton

James D Allen

Selim Bilgin

Geoffrey A Gould

Brinkley Sprunt

Wen Han Wang

Darrell D Buggs

A method and apparatus are provided for entering and exiting multiple threads within a multithreaded processor. A state machine is maintained to indicate a respective status of an associated thread of multiple threads being executed within a multithreaded processor. A change of status for a first thread within the multithreaded processor is detected and, responsive to the change of status for the first thread within the multithreaded processor, a partitioning scheme for the functional unit is altered to service a second thread, but not the first thread, within the multithreaded processor when the change of the status of the first thread comprises a transition from an active state to an inactive state.

Alteration of functional unit partitioning scheme in multithreaded processor based upon thread statuses

A system includes a multithreaded processor, a memory to store the plurality of threads, and a bus to deliver the plurality of threads to the multithreaded processor. The multithreaded processor includes an event detector to detect a first event indication for a first thread. The event detector, responsive to the detection of the first event indication for the first thread, monitors a second thread being processed within the multithreaded processor to detect a clearing point for the second thread and, responsive to the detection of the clearing point for the second thread clears a functional unit within the multithreaded processor for at least the first thread.

Method and apparatus for processing an event occurrence within a multithreaded processor

A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store a long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.

Multi-threading techniques for a processor utilizing a replay queue

A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a replay queue coupled to the checker for temporarily storing one or more instructions for replay. The replay queue may be used to store a long latency instruction, such as a load in which data must be retrieved from an external memory device. The long latency instruction and possibly one or more dependent instruction are stored in the replay queue until the long latency instruction is ready to be executed (e.g., data for the load instruction has been retrieved from external memory). Once the long latency instruction is ready to be executed, (e.g., the data is available), the long latency instruction may then be unloaded from the replay queue for re-execution.

Processor with a replay system that includes a replay queue for improved throughput

A processor includes a memory execution unit for executing load and store instructions and a replay system for replaying instructions which have not executed properly. The memory execution unit including an invalid store flag that is set for a store instruction if the replay system detects that the store instruction has not executed properly and is cleared if the store instruction has executed properly. If an invalid store flag is set for a store instruction, the replay system replays load instructions which are programmatically younger than the invalid store instruction until the store instruction executes properly.

Interface to a memory system for a processor having a replay system

A method includes detecting a first pending event related a first thread being processed within a multithreaded processor. Responsive to the detection of the first pending event, a second thread being processed within the multithreaded processor is monitored to detect an event handling point for the second thread. Responsive to the detection of the event handling point for the second thread, at least a first event handler is invoked to handle at least the first pending event.

Method and apparatus for processing an event occurrence for a least one thread within a multithreaded processor

A method includes maintaining a state machine to provide a multi-bit output, each bit of the multi-bit output indicating a respective status for an associated thread of multiple threads being executed within a multithreaded processor. Status for a first thread is detected, responsive to which a functional unit within the multithreaded processor is configured in accordance with the multi-bit output of the state machine.

Method and apparatus for entering and exiting multiple threads within a multithreaded processor

Storing of instructions relating to a stalled thread

A technique is provided for breaking a stalled condition or livelock in a processor having a replay queue. A livelock or stalled condition is detected. One or more instructions are temporarily stored in a replay queue. A release or break in the livelock or stalled condition is detected, and the instructions are then unloaded from the replay queue for replay or re-execution. For a multi-threaded processor, a stall is detected in one of the threads. Instructions of the stalled thread are temporarily stored in a replay queue, except the oldest instruction of the stalled thread which is allowed to replay or re-execute. This allows other threads to have access to execution and replay resources. Eventually, the oldest instruction will execute and retire, which breaks or releases the stalled thread. The instructions stored in the replay queue are then unloaded from the replay queue.

Processor including replay queue to break livelocks

A method and apparatus to monitor the performance of a processor. A performance specifier specifies a performance data corresponding to the performance. The performance data includes an event and an instruction causing the event. A tag generator is coupled to the performance specifier to generate a performance tag associated with the instruction. The performance tag is stored in a storage. A retirement performance monitor is coupled to the storage to extract the performance tag when the instruction is retired.

Method and apparatus to monitor the performance of a processor

A method includes detecting a first event occurrence for a first thread being processed within a multithreaded processor. Responsive to the detection of this first event occurrence, a second thread being processed within the multithreaded processor is monitored to detect a clearing point for this second thread. Responsive to the detection of a clearing point for the second thread, a functional unit within the multithreaded processor is cleared of data for both the first and the second threads.

A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.

Multi-threading for a processor utilizing a replay queue

A method and apparatus for scheduling operations using a dependency matrix. A child operation, such as a micro-operation, is received for scheduling. The child operation is dependent on the completion of a parent operation, such as when one of the child operation's sources is the parent operations's destination. An entry corresponding to the child operation is placed in a scheduling queue and the child operation is compared with other entries in the scheduling queue. The result of this comparison is stored in a dependency matrix. Each row in the dependency matrix corresponds to an entry in the scheduling queue, and each column corresponds to a dependency on an entry in the scheduling queue. Entries in the scheduling queue can then be scheduled based on the information in the dependency matrix, such as when the entire row associated with an entry is clear.

Scheduling operations using a dependency matrix

A computer processor that has a checker for receiving an instruction. The checker includes a scoreboard, an input for receiving an external replay signal, and decision logic coupled to the scoreboard and the input. The decision logic determines whether the instruction executed correctly based on both the scoreboard and the external replay signal.

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Portland, OR, United States of America

Amit A Merchant