Infineon Technologies Austria Ag

Infineon Technologies Ag

Amirul Afiq Hud

Teck Sim Lee

Ralf Otremba

Bernd Schmoelzer

Xaver Schloegel

Uwe Kirchner

Chooi Mei Chong

Lee Shuang Wang

Franz Stueckler

Fabian Schnoy

Felix Grawert

Edward Fuergut

Josef Hoeglauer

Klaus Schiess

Matthias Strassburg

Thomas Stoek

Stefan Macheiner

Chiew Li Tai

Edmund Sales Cabatbat

Guenther Lohmann

Mohd Kahar Bajuri

Norbert Joson Santos

Hwee Yin Low

Wei Hing Tan

Gaylord Evangelista Cruz

Chin Wei Yang

A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals for blocking a blocking voltage. A lead frame structure electrically and mechanically couples the package to a support and includes an outside terminal extending out of the package footprint side and/or the sidewalls, and is electrically connected with the first load terminal. A top layer arranged at the package top side is electrically connected with the second load terminal. A creepage length between the electrical potential of the outside terminal and the electrical potential of the top layer is defined by a package body surface contour. The surface contour is formed at least by the package top side and package sidewall. At least one structural feature also forms the surface contour is configured to increase the creepage length.

SMD package with top side cooling

A device may include a carrier, a semiconductor chip arranged over a first surface of the carrier, and an encapsulation body comprising six side surfaces and encapsulating the semiconductor chip. A second surface of the carrier opposite to the first surface of the carrier is exposed from the encapsulation body. The device may further include electrical contact elements electrically coupled to the semiconductor chip and protruding out of the encapsulation body exclusively through two opposing side surfaces of the encapsulation body which have the smallest surface areas of all the side surfaces of the encapsulation body, and an electrically insulating layer arranged over the exposed second surface of the carrier.

Semiconductor devices with improved thermal and electrical performance

A semiconductor chip package includes a semiconductor chip disposed over a main surface of a carrier. An encapsulation body encapsulates the chip. First electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a first side face of the encapsulation body. Second electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a second side face of the encapsulation body opposite the first side face. A first group of the first electrical contact elements and a second group of the first electrical contact elements are spaced apart by a distance D that is greater than a distance P between adjacent first electrical contact elements of the first group and between adjacent first electrical contact elements of the second group. The distances D and P are measured between center axes of electrical contact elements.

Semiconductor chip package having a repeating footprint pattern

In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element. The device also includes a low-side semiconductor die including at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference voltage element. The device includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and to a respective low-side transistor of the at least two low-side transistors.

Semiconductor package for multiphase circuitry device

A method of forming a semiconductor device package includes providing a lead frame having a peripheral structure and a heat slug having an upper and lower surface, the heat slug being attached to the peripheral structure. A semiconductor die is attached to the heat slug. The semiconductor die is encapsulated with a molding compound while the heat slug is attached to the peripheral structure. The heat slug is completely devoid of fasteners before the encapsulating.

Semiconductor package with heat slug and rivet free die attach area

The semiconductor chip package comprises a semiconductor chip, and an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises a semiconductor chip; an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises two opposing main faces and side faces which connect the two main faces with each other, wherein the side face have a smaller surface area than the main faces, respectively, and wherein a marking is provided on at least one of the side faces.

Semiconductor chip package comprising side wall marking

Growing community of inventors

Melaka, Malaysia

Amirul Afiq Hud