Nxp B.v.

Amir Zjajo

Jose De Jesus Pineda De Gyvez

Hendrik Johannes Bergveld

Rodger Frank Schuttert

Alexander Guido Gronthoud

Manuel Jose Barragan Asian

According to a first aspect of the present invention there is provided a signal generation system for generating a predetermined analog signal. The system comprises a clock generator () adapted for generating on the basis of an external clock signal a predetermined clock signal, a signal generator including a first gain stage () and a second gain stage () adapted for providing an overall gain of the signal generator and outputting a stepped analog signal, an analog filter () adapted for filtering the stepped analog signal output by the second gain stage and for outputting the predetermined analog signal, and a first and a second clock mapping units () adapted for receiving the predetermined clock signal, and respectively supplying to the first and second gain stages non-overlapped clock signal, wherein the amount of gain provided by the first and second gain stages is controlled by the non-overlapped clock signals. The present invention further relates to a signal generation method of generating discrete-time periodic analog signals suitable for a built-in self-test, as well as to a test method and system using the same.

Signal generation method and apparatus and test method and system using the same

An integrated circuit comprises a device under test and embedded test circuitry. The embedded test circuitry comprises a plurality of process monitoring sensors, a threshold circuit for comparing the sensor signals with a threshold window having an upper and a lower limit and a digital interface for outputting the threshold circuit signal. The process monitoring sensors comprise circuitry based on the circuit elements of the device under test. This arrangement enables monitoring of circuit element performance, such as transistor properties, using process monitoring sensors which are embedded with the device under test, so that the same process parameter variations apply to the sensors as to the device under test. The sensors preferably match the physical layout of the device under test.

IC testing methods and apparatus

Test vectors for structural testing of an analog circuit are selected by first selecting an initial set of test input vectors for the analog circuit. A set of faults is selected, comprising faults that each correspond to a respective node in the analog circuit and corresponding fault voltage value for that node. A measure of overlap is computed between probability distributions of test output signal values for the analog circuit in response to the test input vectors in the presence and absence of each of the faults from said set of faults respectively, as a function of estimated statistical spread of component and/or process parameter values in the analog circuit. Test input vectors are selected from the initial set of test input vectors for use in testing on the basis of whether the measure of overlap for at least one if the faults is below a threshold value in response to the selected test input vector under control of the test selection computer.

Analog circuit testing and test pattern generation

An integrated circuit (IC) comprises a plurality of analog stages (-), each of the analog stages being conductively coupled to a power supply (-), and being conductively coupled to each other by a signal path (); and a test arrangement for testing the plurality of analog stages, the test arrangement comprising input means such as an analog bus () coupled to a signal path input of each analog stage from the plurality of analog stages, output means such as a further analog bus () for communicating a test result to an output of the integrated circuit, switching means such as a plurality of switches () in the biasing infrastructure of the IC for selectively disabling an analog stage, and control means such a shift register () for controlling the switching means. Consequently, the analog stages of the IC can be tested and debugged in isolation without the need for switches in the signal path through the cores. A current sensor () may be present in the power supply to facilitate structural testing of the analog stages in isolation.

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Eindhoven, Netherlands

Amir Zjajo