Kla Tencor Corporation

Kla-tencor Technologies Corporation

Applied Materials, Inc.

Amir Widmann

John Charles Robinson

Michael E Adel

Dongsub Choi

Allen Park

Ellis Chang

Pavel Izikson

Mike Adel

Anat Marchelli

John Fielden

DongSub Choi

Amnon Manassen

Ady Levy

Mark Ghinovker

Daniel Kandel

Yoram Uziel

Mark Davis Smith

Eran Amit

Kris Bhaskar

Nuriel Amir

Guy Cohen

Mark Wagner

Frank Laske

Zain Saidin

Dana Klein

David Yogev

David Tien

Songnian Rong

Nimrod Shuall

Elyakim Kassel

Brad Eichelberger

Gino Marcuccilli

Atsuhiko Kato

Mike Pochkowski

Robert Hardister

Dror Francis

Pati Sekula

Mark Smith

Various methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers are provided. One method for creating a dynamic sampling scheme for a process during which measurements are performed on wafers includes performing the measurements on all of the wafers in at least one lot at all measurement spots on the wafers. The method also includes determining an optimal sampling scheme, an enhanced sampling scheme, a reduced sampling scheme, and thresholds for the dynamic sampling scheme for the process based on results of the measurements. The thresholds correspond to values of the measurements at which the optimal sampling scheme, the enhanced sampling scheme, and the reduced sampling scheme are to be used for the process.

Methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers

Various methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers are provided. One method for creating a dynamic sampling scheme for a process during which measurements are performed on wafers includes performing the measurements on all of the wafers in at least one tot at all measurement spots on the wafers. The method also includes determining an optimal sampling scheme, an enhanced sampling scheme, a reduced sampling scheme, and thresholds for the dynamic sampling scheme for the process based on results of the measurements. The thresholds correspond to values of the measurements at which the optimal sampling scheme, the enhanced sampling scheme, and the reduced sampling scheme are to be used for the process.

Universal target based inspection drive metrology includes designing a plurality of universal metrology targets measurable with an inspection tool and measurable with a metrology tool, identifying a plurality of inspectable features within at least one die of a wafer using design data, disposing the plurality of universal targets within the at least one die of the wafer, each universal target being disposed at least proximate to one of the identified inspectable features, inspecting a region containing one or more of the universal targets with an inspection tool, identifying one or more anomalistic universal targets in the inspected region with an inspection tool and, responsive to the identification of one or more anomalistic universal targets in the inspected region, performing one or more metrology processes on the one or more anomalistic universal metrology targets with the metrology tool.

Method and system for universal target based inspection and metrology

An apparatus includes a dedicated material handling module having a dedicated automated material handling system (AMHS) defines a transport route between a first tool and a second tool selected from a plurality of tools in a fabrication facility. The dedicated AMHS is configured to transport wafer carriers between the first tool and the second tool or vice versa independent of a fabrication facility AMHS that is configured to transport wafer carriers among the plurality of tools.

Material handling with dedicated automated material handling system

Aspects of the present disclosure describe systems and methods for calibrating a metrology tool by using proportionality factors. The proportionality factors may be obtained by measuring a substrate under different measurement conditions. Then calculating the measured metrology value and one or more quality merits. From this information, proportionality factors may be determined. Thereafter the proportionality factors may be used to quantify the inaccuracy in a metrology measurement. The proportionality factors may also be used to determine an optimize measurement recipe. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Method for estimating and correcting misregistration target inaccuracy

Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.

Inspection guided overlay metrology

A method and apparatus for process control in a lithographic process are described. Metrology may be performed on a substrate either before or after performing a patterning process on the substrate. One or more correctables to the lithographic patterning process may be generated based on the metrology. The patterning process performed on the substrate (or a subsequent substrate) may be adjusted with the correctables.

Feedforward/feedback litho process control of stress and overlay

Methods for inspecting a wafer and/or predicting one or more characteristics of a device being formed on a wafer are provided. One method includes acquiring images for multiple die printed on a wafer, each of which is printed by performing a double patterning lithography process on the wafer and which include two or more die printed at nominal values of overlay for the double patterning lithography process and one or more die printed at modulated values of the overlay; comparing the images acquired for the multiple die printed at the nominal values to the images acquired for the multiple die printed at the modulated values; and detecting defects in the multiple die printed at the modulated values based on results of the comparing step.

Inspecting a wafer and/or predicting one or more characteristics of a device being formed on a wafer

A combined metrology mark, a system, and a method for calculating alignment on a semiconductor circuit are disclosed. The combined metrology mark may include a mask misregistration structure and a wafer overlay mark structure.

Unique mark and method to determine critical dimension uniformity and registration of reticles combined with wafer overlay capability

A method for automatic process control (APC) performance monitoring may include, but is not limited to: computing one or more APC performance indicators for one or more production lots of semiconductor devices; and displaying a mapping of the one or more APC performance indicators to the one or more production lots of semiconductor devices.

Advanced process control optimization

A method and apparatus for process control in a lithographic process are described. Metrology may be performed on a substrate either before or after performing a lithographic patterning process on the substrate. One or more correctables to the lithographic patterning process may be generated based on the metrology. The lithographic patterning process performed on the substrate (or a subsequent substrate) may be adjusted with the correctables.

Disclosed are apparatus and methods for optimizing a metrology tool, such as an optical or scanning electron microscope so that minimum human intervention is achievable during the optimization. In general, a set of specifications and an initial input data are initially provided for a particular target. The specifications provide limits for characteristics of images that are to be measured by the metrology tool. The metrology tool is then automatically optimized for measuring the particular target so as to meet one or more of the provided specifications without further significant human intervention with respect to the metrology tool. In one aspect, the input data provided prior to the automated optimization procedure includes a plurality of target locations and a synthetic image of the particular target.

Waferless recipe optimization

Computer-implemented methods, carrier media, and systems for creating a metrology target structure design for a reticle layout are provided. One computer-implemented method for creating a metrology target structure design for a reticle layout includes simulating how one or more initial metrology target structures will be formed on a wafer based on one or more fabrication processes that will be used to form a metrology target structure on the wafer and one or more initial metrology target structure designs. The method also includes creating the metrology target structure design based on results of the simulating step.

Computer-implemented methods, carrier media, and systems for creating a metrology target structure design for a reticle layout

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Sunnyvale, CA, United States of America

Amir Widmann